Notched Leadframe Fingers for Stackable Semiconductor Die Interconnects
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Solution Overview
Problem
The complexity and cost of manufacturing stackable fan-out wafer level chip scale packages (Fo-WLCSPs) are increased due to the need for complex redistribution layers and time-consuming processes like lithography, etching, and metal deposition for electrical interconnects.
Innovation Solution
A method involving a leadframe with notched fingers is used for stacking semiconductor die, where a semiconductor die is mounted between the notched fingers, a bond wire is formed between a contact pad and a finger, and an encapsulant is deposited over the die and fingers, simplifying the electrical interconnect process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex redistribution layers with lithography, etching, and metal deposition are used for electrical interconnects in stackable Fo-WLCSPs, then electrical connectivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the complex redistribution layer process from the manufacturing flow. Instead of forming complete RDL structures with multiple lithography, etching, and deposition steps, the invention uses simplified leadframe fingers with notches that directly provide electrical interconnect functionality, removing the disturbing complex manufacturing steps while maintaining electrical connectivity
Solution Approach 2:
The patent employs a disposable leadframe structure with notched fingers that serves the electrical interconnect function temporarily during assembly and then becomes part of the final package. This approach replaces expensive, complex RDL manufacturing with a simpler, cost-effective leadframe-based solution that achieves the same electrical connectivity goal without requiring sophisticated fabrication processes
2Reliability
If complex redistribution layers are used for electrical interconnects, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent employs a disposable leadframe structure with notched fingers that serves the electrical interconnect function temporarily during assembly and then becomes part of the final package. This approach replaces expensive, complex RDL manufacturing with a simpler, cost-effective leadframe-based solution that achieves the same electrical connectivity goal without requiring sophisticated fabrication processes
Solution Approach 2:
The patent extracts and eliminates the complex redistribution layer process from the manufacturing flow. Instead of forming complete RDL structures with multiple lithography, etching, and deposition steps, the invention uses simplified leadframe fingers with notches that directly provide electrical interconnect functionality, removing the disturbing complex manufacturing steps while maintaining electrical connectivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies and cost-effectively provides electrical interconnects for stackable Fo-WLCSPs, reducing manufacturing complexity and costs by eliminating the need for complex redistribution layers.
Implementation Method 1
forming a bond wire between a first contact pad on the first semiconductor die and notched finger
Implementation Method 2
depositing an encapsulant over the first semiconductor die and notched fingers
Data Source
AI summary
A semiconductor device has a leadframe with first and second opposing surfaces and a plurality of notched fingers. The leadframe is mounted to a carrier. A first semiconductor die is mounted over the carrier between the notched fingers. Conductive TSVs are formed through the first semiconductor die. A bond wire is formed between a first contact pad on the first semiconductor die and notched finger. The conductive TSV are electrically connected to the bond wires. An encapsulant is deposited over the first semiconductor die and notched fingers. Bumps are formed over the first surface of the leadframe. The carrier is removed and the leadframe is singulated. The leadframe and first semiconductor die is mounted to a substrate. A second semiconductor die is mounted to a second contact pad on the first semiconductor die. A third semiconductor die is mounted to the second surface of the leadframe.