Notched Mesa FET Gate Layout for Lower RF Parasitics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
At high frequencies, Field Effect Transistor (FET) performance is hindered by parasitic resistance, inductance, and capacitance due to the extended gate electrode beyond the active channel region, which negatively impacts power, gain, and efficiency.
Innovation Solution
The introduction of notches in the mesa structure of the FET reduces gate parasitics by eliminating extra gate length over the active region, allowing the gate tab to be positioned closer to the active inner portion, and the use of a multi-fingered gate structure further enhances performance by minimizing parasitic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode extends beyond the active channel region to provide sufficient gate control, then the gate control over carrier conduction is improved, but parasitic gate resistance, inductance, and capacitance increase negatively affecting high frequency operation
Solution Approach 1:
The gate electrode is segmented into multiple fingers that extend into the active channel region, rather than using a single continuous gate. This segmentation allows the gate to provide sufficient control over the carrier conduction path while reducing the overall parasitic inductance and resistance by dividing the current path into multiple parallel paths.
Solution Approach 2:
The gate electrode structure transitions from a planar two-dimensional layout to a three-dimensional configuration where gate fingers extend vertically and laterally into the active channel region. This dimensional change enables the gate to achieve both sufficient control coverage and reduced parasitics by utilizing spatial arrangement rather than simply extending gate length in one direction.
2Speed
If the gate channel width is narrowed to reduce electron transfer time for high frequency operation, then the operating frequency is improved, but the contribution of carriers in the gate channel region becomes stronger increasing parasitic effects
Solution Approach 1:
The gate channel is segmented into multiple narrow fingers rather than using a single wide channel. This segmentation maintains the short electron transfer distance required for high frequency operation while distributing the carrier conduction across multiple paths, thereby reducing the overall parasitic effects that would result from a single narrow channel.
Solution Approach 2:
Different regions of the gate structure have different properties: the gate fingers have narrow widths optimized for fast electron transfer, while the spacing and arrangement of fingers are optimized to minimize parasitic interactions. This local optimization allows simultaneous achievement of high speed and low parasitics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves the RF performance of FETs at high frequencies by reducing parasitic components and optimizing carrier conduction, especially in multi-gate finger configurations.
Implementation Method 1
a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure
Implementation Method 2
a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa structure
Data Source
Figure 1A
Figure 1B~1C
Figure 2A
AI summary
A Field Effect Transistor structure includes: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa; and a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure. In one embodiment, the mesa structure includes a pair of notches projecting inwardly towards each other and the inner portion of the gate extends longitudinally between the pair of notches.