Notebook SoC Architecture for TDP-Limited AI Compute
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Solution Overview
Problem
Conventional system on chips (SoCs) are limited by form factor, power supply, and thermal considerations, constraining their performance in user devices such as laptops.
Innovation Solution
The SoC incorporates multiple CPU core complexes with asymmetric last level caches, a parallel processor, and an inference processing unit, along with a scalable control and data fabric, advanced clocking, and power gating techniques to optimize performance within a given form factor and thermal design power envelope.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple CPU core complexes with asymmetric last level caches, parallel processor, and inference processing unit are incorporated into the SoC, then computational capabilities and performance are improved, but the form factor and thermal design power envelope are exceeded
Solution Approach 1:
The SoC is divided into multiple CPU core complexes (first CCX with 4 cores, second CCX with 8 cores), each with dedicated last level caches. This segmentation allows the system to achieve high computational capabilities through distributed processing while keeping each individual core complex compact, thus managing the overall form factor constraint.
Solution Approach 2:
The patent implements nested cache hierarchies where each CPU core complex has its own dedicated last level cache, and these caches are integrated within the core complex structures. The inference processing unit is also integrated within the SoC substrate. This nesting approach maximizes computational density within the available area by efficiently organizing memory hierarchies.
2Productivity
If multiple CPU core complexes with asymmetric last level caches, parallel processor, and inference processing unit are incorporated into the SoC, then computational capabilities and performance are improved, but the thermal design power envelope is exceeded
Solution Approach 1:
The patent implements dynamic power management through selective activation of different CPU core complexes based on workload requirements. The system can activate only the necessary number of cores (e.g., first CCX with 4 cores or second CCX with 8 cores) rather than all cores continuously, enabling the SoC to adapt power consumption to match actual computational needs while maintaining high peak performance when required.
Solution Approach 2:
The asymmetric cache configuration changes the memory access parameters for different core complexes, with the first CCX having a 16 MB LLC and the second CCX having an 8 MB LLC. This parameter optimization improves memory access efficiency and reduces overall power consumption by minimizing cache misses and optimizing data retrieval patterns.
3Area of stationary object
If conventional SoC design is used, then form factor and power supply constraints are satisfied, but performance is constrained
Solution Approach 1:
The patent employs asymmetric cache sizes for different CPU core complexes (16 MB for first CCX, 8 MB for second CCX) to optimize performance based on specific workload characteristics. This asymmetric design allows each core complex to be tuned for particular workloads, achieving higher overall system performance while maintaining compact form factor through efficient space utilization.
Solution Approach 2:
The patent introduces a new dimension to the traditional von Neumann architecture by integrating an inference processing unit directly into the SoC substrate, creating a multi-dimensional processing architecture that handles different types of computational tasks simultaneously in different processing domains.
4Power
If selective activation of SoC components is enabled, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The scalable control fabric implements feedback mechanisms that monitor workload characteristics and dynamically adjust which CPU core complexes and processing units are activated. This feedback-driven approach enables intelligent power management by activating only the necessary computational resources based on real-time system state, reducing power consumption while managing complexity through automated decision-making.
Data Source
AI summary
A system on chip is configured to operate within a thermal design power (TDP) envelope threshold and form factor (e.g., a TDP envelope and form factor associated with a 10 watt to 15 watt notebook or tablet). The system on chip includes a plurality of central processing unit (CPU) core complexes, each CPU core complex including a last level cache; a parallel processor including a plurality of shader arrays; and an inference processing unit (IPU) including a plurality of inference processing engines (IPEs).