Direct N/P Local Interconnect With Reduced STI Recess Capacitance
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Solution Overview
Problem
Conventional semiconductor devices with excessive recess on shallow trench isolation (STI) oxide suffer from high coupling capacitance, which degrades AC performance by increasing capacitive coupling with active gates.
Innovation Solution
The proposed solution involves forming local interconnects with reduced recess depths, using an etch stop layer and potentially replacing STI oxide with low-k dielectric in the recess region to minimize capacitive coupling, thereby improving AC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If excessive recess is formed on STI oxide to create local interconnect, then electrical stress relief and current path improvement are achieved, but coupling capacitance increases significantly degrading AC performance
Solution Approach 1:
The patent applies local quality by creating different recess depths in different regions of the local interconnect. Specifically, the interconnect structure has varying depths: deeper regions provide electrical stress relief and current path benefits, while shallower regions minimize coupling capacitance with active gates. This spatial variation in depth allows each region to optimize for its specific function.
Solution Approach 2:
The local interconnect is segmented into multiple depth regions rather than being uniformly recessed. The structure divides the interconnect into deeper portions (for stress relief and current flow) and shallower portions (for reduced capacitance), allowing independent optimization of each segment's depth to balance electrical performance and AC characteristics.
2Productivity
If deeper recess is formed in local interconnect, then current density and electrical stress are improved, but capacitive coupling with active gates increases
Solution Approach 1:
The interconnect structure implements local quality by varying the recess depth across different spatial regions. Deeper recesses are positioned where high current density and stress relief are needed, while shallower recesses are positioned near active gates where capacitive coupling must be minimized. This localized depth control allows simultaneous optimization of current flow and capacitance reduction.
3Object-affected harmful factors
If reduced recess depth is used in local interconnect, then coupling capacitance is decreased improving AC performance, but electrical stress relief capability is reduced
Solution Approach 1:
The local interconnect is segmented into functional zones with different recess depths. Shallower segments reduce coupling capacitance with active gates for improved AC performance, while deeper segments maintain electrical stress relief capability. This segmentation allows the structure to simultaneously provide both capacitance reduction and stress management functions.
Solution Approach 2:
Different regions of the interconnect are given different depth qualities according to their functional requirements. Regions adjacent to active gates use shallower recesses to minimize capacitive coupling, while regions requiring stress relief use deeper recesses. This local differentiation of depth quality enables the structure to optimize both AC performance and electrical stress relief.
Data Source
AI summary
Disclosed are devices that include a direct N/P local interconnect with minimal recess on shallow trench isolation (STI) oxide. This reduces undesirable coupling capacitance with active gate, which in turn improves AC performance of the device. Pull or even partial replacement of STI oxide with low-k dielectric can further reduce coupling capacitance.