Multi-Die FPGA Power Gating for Scalable Network Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current FPGA implementations for network processing, such as those using multiple FPGA chips, face challenges in scalability, port density, and wire speed throughput, leading to high power consumption and costly development processes compared to ASIC and ASSP devices.
Innovation Solution
A multi-die device comprising interconnected FPGA dies, a network interface controller die, and memory dies, with through-silicon vias or organic substrates, and a function scheduler that monitors and gates power to unused processing elements to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple FPGA chips are used for network processing, then scalability and port density are improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent combines multiple FPGA dies and NIC dies onto a single package substrate, creating an integrated multi-die device. This merging approach achieves the scalability and port density benefits of multiple devices while reducing overall power consumption by eliminating redundant packaging and interconnections, and enabling shared power management resources.
Solution Approach 2:
The patent transitions from a single-die architecture to a multi-die stacked architecture, adding the vertical dimension through 3D integration. This allows multiple FPGA and NIC functional blocks to be stacked in different layers, achieving high port density and scalability while maintaining compact form factor and reduced power consumption compared to traditional multi-chip solutions.
2Adaptability or versatility
If multiple FPGA chips are used for network processing, then port density is improved, but device complexity and development cost increase
Solution Approach 1:
The patent integrates multiple FPGA dies and NIC dies into a single packaged device with unified interconnections through the package substrate. This merging eliminates the need for complex external routing and inter-chip communication infrastructure, reducing system-level device complexity while achieving high port density through the integrated architecture.
3Speed
If hardware resources are continuously powered for network processing, then processing speed is maintained, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management within the multi-die device, allowing individual FPGA and NIC functional blocks to be powered on or off based on operational requirements. This dynamic control enables the system to maintain processing speed when needed while reducing power consumption during idle periods or when certain functions are not required.
Solution Approach 2:
The patent employs periodic monitoring and power gating of hardware resources, where the system periodically assesses which FPGA and NIC blocks are actively being used and adjusts power supply accordingly. This periodic action ensures that processing speed is maintained for active functions while power is conserved by gating unused resources.
Data Source
AI summary
Systems and methods are provided for reducing power consumption of a multi-die device, such as a network processor FPGA (npFPGA). The multi-die device may include hardware resources such as FPGA dies, which may be coupled to NIC dies and/or memory dies. Power consumption of the multi-die device may be reduced by monitoring usage of hardware resources in the multi-die device, identifying hardware resources that are not in use, and gating power to the identified hardware resources. The status of processing elements (PEs) in the multi-die device may be tracked in a PE state table. Based on the PE state table, tasks from a task queue may be assigned to one or more processing elements.