N-polar GaN Transistor Linearity via Integrated Derivative Cancellation
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Solution Overview
Problem
Existing derivative cancellation techniques for transistors become less effective at mm-wave frequencies due to parasitics associated with combining multiple discrete devices, leading to reduced linearity and increased parasitic inductance.
Innovation Solution
The integration of derivative cancellation directly into a single N-polar III-nitride transistor device by varying the threshold voltage across the gate width, using etch stop layers to establish multiple threshold voltages, and optimizing the gate and cap layer structures to minimize parasitic inductance and enhance linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple discrete devices are used for derivative cancellation, then linearity is improved, but parasitic inductance increases and effectiveness is reduced at mm-wave frequencies
Solution Approach 1:
The patent merges multiple discrete devices into a single integrated transistor device with multiple gates. The first and second gates are formed on the same semiconductor substrate and work together to achieve derivative cancellation, eliminating the parasitic inductance associated with combining separate devices while maintaining the linearity benefits of derivative cancellation techniques
Solution Approach 2:
The patent segments the gate function into multiple independent gates (first gate and second gate) that can be controlled separately. Each gate controls a portion of the channel, allowing independent adjustment of threshold voltages to achieve derivative cancellation while keeping all gates within a single device structure to minimize parasitics
2Reliability
If threshold voltage is varied across gate width, then linearity is improved through derivative cancellation, but device complexity increases
Solution Approach 1:
The patent applies local quality by creating regions with different threshold voltages within the same device. The first gate and second gate create distinct regions in the channel with different electrical characteristics, allowing derivative cancellation to be achieved through spatial variation of threshold voltage while maintaining a relatively simple overall device structure
Solution Approach 2:
The patent achieves multi-functionality by having a single transistor device perform both the function of multiple discrete devices for derivative cancellation and maintain compact integration. The multiple gates within one device provide both the threshold voltage variation needed for linearity and the compact structure needed to minimize parasitics
Data Source
AI summary
Derivative cancellation techniques have been used to linearize transistors using multiple discreet devices. However at frequencies approaching and in the mm-wave regime the use of individual devices no longer works due to the parasitics associated with combining the devices. In this invention device structures are described which apply the derivative cancellation technique in a single device thus removing the detrimental impact of combining. In one example, an N-polar transistor structure includes a channel; a cap structure comprising a plurality of cap layers on or above the channel; a source contact and a drain contact to the channel; and a castellated, stepped, or varying pattern formed in the cap layers so that gate metal deposited on the pattern forms at least two different threshold voltages and current combines in the ohmic region with essentially zero parasitic inductance.