NPU and Hardware-Accelerated Forwarding for High-Speed Network Tests

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Solution Overview

Problem

Traditional TCP-based network speed test applications underestimate actual network speed, while UDP-based tests on CPUs face resource constraints and latency issues, limiting their ability to meet high-speed network requirements.

Innovation Solution

A network device utilizing a network processing unit (NPU) and hardware acceleration circuit separates the control plane from the data plane, offloading data processing to the NPU and hardware acceleration circuit, reducing CPU intervention and utilizing on-chip memory for faster packet transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If UDP-based network speed test application runs on CPU, then network speed measurement can be performed, but CPU resource consumption increases and packet transmission speed is limited

Engineering Contradiction:

Improvenetwork speed measurement accuracyVSAvoidpacket transmission speed

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The system segments the network speed test function into two independent parts: the control plane (CPU) handles test initiation and coordination, while the data plane (NPU + hardware acceleration circuit) handles actual packet generation and transmission. This segmentation allows parallel processing without CPU bottleneck, resolving the contradiction between measurement capability and transmission speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The NPU acts as an intermediary between the CPU and the hardware acceleration circuit. It receives control instructions from the CPU, then independently manages packet generation and coordinates with the hardware acceleration circuit for transmission, eliminating the need for frequent CPU intervention and improving packet transmission speed.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If packet buffer is allocated in off-chip memory (DRAM), then sufficient buffering capacity is available, but access latency increases and packet transmission speed decreases

Engineering Contradiction:

Improvepacket buffer capacityVSAvoidDRAM access latency

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The system implements a nested memory structure where a small on-chip memory (SRAM) is embedded within the NPU, which itself is part of the larger system containing off-chip DRAM. The SRAM provides low-latency buffering for active packet processing, while DRAM provides bulk storage capacity. This nested arrangement allows the system to benefit from both fast access (SRAM) and large capacity (DRAM) simultaneously.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS20250300922A1Network device using network processing unit and hardware acceleration circuit to meet speed test requirements of high-speed network and associated network speed test method

Publication Date: 2025.09.25 AIROHA TECH (SUZHOU) LTD

AI summary

A network device includes a storage device, a central processing unit (CPU), a hardware acceleration circuit, and a network processing unit (NPU). The storage device stores program codes. The CPU loads and executes the program codes to deal with a control function of a network speed test. The hardware acceleration circuit provides hardware-accelerated packet forwarding. The NPU interacts with the control function performed by the CPU, and deals with processing of data packets used for the network speed test. Transmission of the data packets between the network device and another network device is performed through the NPU and the hardware acceleration circuit, without intervention of the CPU.