NPU Clock Phase Calibration for Power Stability

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Solution Overview

Problem

The instantaneous power consumption of neural processing units (NPUs) surges due to significant computational operations in certain layers of artificial neural networks, leading to instability in supply voltage and increased power consumption.

Innovation Solution

A neural processing unit (NPU) is designed with a circuit configuration that includes multiple groups of processing elements, a clock signal output circuit, a power measurement circuit, and a phase calibration circuit. This configuration dynamically adjusts the phase of clock signals based on the ratio of peak power to average power, thereby stabilizing the supply voltage and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of processing elements in the neural processing unit is increased to improve parallel processing performance, then the computational speed for artificial intelligence is enhanced, but the instantaneous power consumption surges and supply voltage stability deteriorates

Engineering Contradiction:

Improvecomputational speedVSAvoidinstantaneous power consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic frequency adjustment where the drive frequency of processing elements is varied based on real-time power consumption levels. When instantaneous power consumption exceeds a threshold, the frequency is reduced to stabilize supply voltage, and when power consumption is within acceptable ranges, the frequency is increased to maximize computational performance. This dynamic adaptation resolves the contradiction between maintaining high productivity and controlling energy usage.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of processing elements by adjusting their drive frequency in response to power consumption conditions. By modifying the frequency parameter dynamically, the system can operate at high performance levels when power is available and reduce power consumption when instantaneous demands surge, thus resolving the contradiction between computational speed and power usage.

Inventive Principle:

Principle #35Parameter changes

2Speed

If the drive frequency of the neural processing unit is increased to improve processing speed, then the parallel processing performance is enhanced, but the supply voltage stability deteriorates due to increased instantaneous power demand

Engineering Contradiction:

Improveprocessing speedVSAvoidsupply voltage stability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent employs a feedback mechanism where power consumption is continuously monitored and used to adjust the drive frequency of processing elements. When power consumption indicates potential voltage instability, the frequency is reduced to maintain supply voltage stability. This closed-loop control resolves the contradiction by allowing high processing speeds only when voltage stability can be maintained.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts the drive frequency based on real-time power consumption and voltage stability conditions. Rather than operating at a fixed high frequency, the processing elements adapt their speed to maintain voltage stability, thus resolving the contradiction between achieving high processing speed and ensuring supply voltage reliability.

Inventive Principle:

Principle #15Dynamics

3Productivity

If the number of processing elements is increased to handle large computational operations, then the artificial neural network processing capability is improved, but the capacitance of the power supply unit becomes insufficient to handle peak power supply

Engineering Contradiction:

Improveprocessing capabilityVSAvoidcapacitance of power supply unit

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements dynamic frequency scaling that reduces the operational frequency of processing elements when peak power supply conditions are detected. This allows the system to support a larger number of processing elements for improved productivity while managing the limited capacitance of the power supply unit by adapting performance to available power capacity in real-time.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250124268A1NPU, soc and electronic device being operated based on dynamically calibrated phase of clock signal

Publication Date: 2025.04.17 DEEPX CO LTD

AI summary

A neural processing unit may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of groups of processing elements (PEs) including a plurality of PEs; a second circuit arranged to output a plurality of clock signals to the first circuit; a third circuit configured to measure a ratio of peak power and average power of at least the first circuit; and a fourth circuit, arranged to dynamically calibrate a phase of at least one of the plurality of clock signals of the second circuit based on the ratio of peak power and average power measured in the third circuit.