Multi-Phase Clock Distribution for NPU Peak Power Reduction
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Solution Overview
Problem
Neural processing units (NPUs) face challenges in stabilizing supply voltage fluctuations due to peak power surges, leading to increased power consumption and potential system instability, especially when handling varying computational demands across different layers of artificial neural network operations.
Innovation Solution
A system-on-chip (SoC) design that includes multiple NPUs operating on distinct clock signals with preset phases, generated by shifting or delaying the original clock signal, to distribute peak power and stabilize supply voltage, thereby reducing overall power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing elements in the neural processing unit is increased to improve parallel processing performance, then the computational speed for artificial intelligence is enhanced, but the instantaneous power consumption surges and supply voltage fluctuates
Solution Approach 1:
The system divides the neural processing workload across multiple NPUs (first NPU and second NPU) that operate on different clock phases. Each NPU processes a portion of the neural network layers independently, segmenting the peak computational demand and distributing it across time and multiple processing units, thereby reducing instantaneous power consumption while maintaining high computational throughput
Solution Approach 2:
The system employs multi-phase clock signals (first clock signal and second clock signal with different phases) to periodically activate processing elements in different NPUs at different times. This periodic activation distributes the computational workload across time phases, preventing simultaneous peak power consumption while maintaining overall processing speed through coordinated parallel operation
2Reliability
If the supply voltage is increased to ensure system stability during peak power demand, then system reliability is maintained, but the power consumption of the neural processing unit increases rapidly
Solution Approach 1:
By using multi-phase clock signals to periodically activate processing elements in different NPUs, the system distributes peak power demand across time phases. This allows the supply voltage to remain stable at lower levels since no single phase requires maximum simultaneous power, thereby maintaining system reliability while reducing overall power consumption
Solution Approach 2:
The system dynamically coordinates the activation of processing elements across multiple NPUs using phase-shifted clock signals. This dynamic time-division multiplexing allows the power supply to deliver controlled, distributed power peaks rather than a single large peak, enabling stable operation at optimized voltage levels that reduce power consumption
Data Source
AI summary
A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.