NPU Functional Safety Test Circuit Without Parity Bit Overhead
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing functional safety (FuSa) tests on integrated circuits fail to meet expected standards and result in high data transmission power consumption and area overhead due to the use of parity checks, which only detect faults in data transmission lines and not operation circuits.
Innovation Solution
A circuit and method that generates configuration information, test data, and compares consistency among processed test data to determine the functional safety of integrated circuits, eliminating the need for parity bits and reducing area overhead and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity check is used for functional safety test, then data transmission line faults can be detected, but operation circuit faults cannot be detected and FuSa standard cannot be met
Solution Approach 1:
The patent segments the testing process into multiple independent test modules, each responsible for testing specific circuits or functions. The test system is divided into a test controller, test data generator, comparator, and multiple test modules that can independently operate. This segmentation allows comprehensive coverage of both data transmission lines and operation circuits without requiring a single complex testing approach.
Solution Approach 2:
The patent creates a universal testing framework where the same test system can detect various types of faults including data transmission line faults and operation circuit faults. The test controller can configure different test modes and the comparator can verify multiple types of data consistency, making the testing system multi-functional and capable of meeting comprehensive FuSa standards.
2Reliability
If parity bit is attached to data for FuSa test, then data transmission line faults can be detected, but area overhead and data transmission power consumption increase greatly
Solution Approach 1:
The patent extracts the parity bit from the data transmission process and replaces it with an independent test data generation system. Instead of attaching parity bits to every data transmission, the system generates test data independently and uses a comparator to verify consistency, thereby eliminating the need for additional parity bits in the data transmission path and reducing power consumption.
Solution Approach 2:
The patent uses a comparator to create a virtual copy of the expected output data and compares it with the actual output data. This copying approach allows fault detection without requiring additional physical parity bits in the transmission path, as the comparison is performed digitally within the test system rather than through redundant transmission bits.
3Reliability
If parity bit is attached to data for FuSa test, then data transmission line faults can be detected, but circuit area overhead increases greatly
Solution Approach 1:
The patent removes the parity bit from the data transmission path and replaces it with a dedicated test data generation and comparison system. This extraction eliminates the need for additional transmission lines and parity bit handling circuitry, thereby reducing the overall circuit area overhead while maintaining comprehensive safety testing capability.
Solution Approach 2:
The patent introduces a comparator as an intermediary component that verifies data consistency without requiring parity bits in the transmission path. The comparator acts as a mediator between the test data generator and the device under test, enabling fault detection through virtual comparison rather than physical redundancy, thus reducing circuit area.
Data Source
AI summary
Disclosed are a circuit and method for performing functional safety test, a neural processing unit, and a storage medium, relating to field of functional safety technology. The circuit for performing functional safety test includes: a configurator, configured for generating and outputting configuration information for testing an integrated circuit (IC) to be tested; a plurality of test data generators, configured for generating and outputting, based on the configuration information, a plurality of first test data corresponding respectively to the test data generators; the integrated circuit to be tested, configured for processing the plurality of first test data, to obtain and output a plurality of second test data; and a first comparator, configured for comparing consistency among the plurality of second test data, to obtain a first test result for the integrated circuit to be tested.