NROM Flash Memory Read Method Using Vcc/n Bitline Pre-Charging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash memory read operations are limited by slow read speed, high power consumption, and noise during decoding changeover, particularly in Nitride Read Only Memory (NROM) cells, which necessitates improving read speed and reducing power usage while minimizing power changes during decoding.
Innovation Solution
A method involving pre-charging even and odd bitlines to Vcc/n and ground respectively, with bitline transistors selectively controlling current sensing on both the source and drain sides of memory cells to determine logical states, allowing for faster pre-charging and reduced power consumption by avoiding power changes during decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional flash memory read operations are used, then the read operation can be performed, but the read speed is slow and power consumption is high
Solution Approach 1:
The patent applies preliminary action by pre-charging the bitlines to Vcc/n voltage before the actual read operation. This pre-charging step prepares the bitlines in advance with the appropriate voltage level, enabling faster subsequent read operations without requiring full Vcc charging during the critical read path, thus improving read speed while reducing overall power consumption.
2Reliability
If conventional decoding operations are performed, then data can be read, but noise is generated during decoding changeover
Solution Approach 1:
The patent applies parameter changes by using Vcc/n voltage instead of full Vcc for pre-charging the bitlines. This voltage parameter modification reduces the power change magnitude during decoding operations, thereby minimizing noise generation during decoding changeover while maintaining sufficient voltage levels for reliable data reading and decoding stability.
Data Source
AI summary
A read operation method is provided for a flash memory array having a plurality of memory cells, wordlines, even bitlines, odd bitlines and a plurality of bitline transistors. The method includes pre-charging the plurality of even bitlines to about Vcc/n and pre-charging the plurality of odd bitlines to ground. The current flowing to/from a first bit location in each of the memory cells is selectively sensed. A logical state is determined from the sensed current for the first bit location in each of the memory cells. The method also includes pre-charging the plurality of odd bitlines to about Vcc/n and pre-charging the plurality of even bitlines to ground. The current flowing to/from a second bit location in each of the memory cells is selectively sensed. A logical state is determined from the sensed current for the second bit location in each of the memory cells.