NROM Memory Cell Vertical MOSFET Structure for High Density Storage
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Solution Overview
Problem
Current memory technologies face challenges in achieving high areal data storage capacity, low power consumption, and fast data access speed, particularly in volatile DRAMs which require frequent refresh operations and consume power to retain data.
Innovation Solution
The development of a memory cell array using vertical metal oxide semiconductor field effect transistors (MOSFETs) with a gate insulator that allows for multiple charge levels to be trapped, enabling the storage of more than one bit per gate and reducing power consumption by operating at reduced drain source current with distinct voltage threshold regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If DRAM memory cells are used to achieve high areal data storage capacity, then area efficiency is improved, but power consumption increases due to frequent refresh operations
Solution Approach 1:
The patent changes the operational parameters of the memory cell by using a vertical MOSFET structure with a gate insulator that can trap multiple charge levels. This allows the memory to operate at reduced drain source current with distinct voltage threshold regions, eliminating the need for frequent refresh operations while maintaining high areal storage capacity
Solution Approach 2:
The patent transitions from a planar memory cell structure to a vertical MOSFET structure. By extending the transistor structure vertically from the substrate with source/drain regions extending upward, the patent achieves high areal density while enabling non-volatile operation through charge trapping in the gate insulator, thereby reducing power consumption
2Quantity of substance
If vertical MOSFET structures with multiple charge levels are used, then data storage density is improved, but device complexity increases
Solution Approach 1:
The gate insulator in the vertical MOSFET structure serves multiple functions: it acts as the gate dielectric for transistor operation and simultaneously serves as a charge trapping layer for non-volatile memory storage. This multi-functionality enables multiple bits to be stored per cell through distinct voltage threshold regions without significantly increasing device complexity
Solution Approach 2:
The patent utilizes the physical property of charge trapping in the gate insulator to create multiple stable charge levels. By controlling the amount of charge trapped in the insulator, distinct voltage threshold regions are formed, enabling multiple bits of data to be stored per memory cell while maintaining a relatively simple vertical MOSFET structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances data storage density and reduces power consumption by allowing multiple bits to be stored per cell, while maintaining fast access speeds and eliminating the need for frequent refresh operations.
Implementation Method 1
a gate insulator that allows for multiple charge levels to be trapped, enabling the storage of more than one bit per gate
Implementation Method 2
operating at reduced drain source current with distinct voltage threshold regions
Data Source
AI summary
An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.