Memory Controller NRPB Status Indicator Polling Optimization
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Solution Overview
Problem
In mass storage systems using non-volatile memory devices, efficiently polling the status of multiple memory banks to determine when they are ready to accept new commands is inefficient, as current methods check all banks regularly, regardless of whether commands are queued or not, leading to wasted resources and reduced performance.
Innovation Solution
Implement a 'Now Ready, Previously Busy' (NRPB) status indicator that combines current and previous Ready/Busy status data to determine if a memory device is ready to accept new commands, allowing polling only when necessary, thereby reducing unnecessary checks and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory banks are polled regularly to check readiness status, then the controller can detect when devices are ready to accept commands, but this approach wastes processing time and resources on banks that are continuously busy
Solution Approach 1:
The patent applies partial action by polling only a subset of memory banks at any given time rather than all banks. The controller identifies which banks are likely to be ready based on command completion tracking and polls only those banks, reducing unnecessary polling operations on banks that are continuously busy or unlikely to be ready.
Solution Approach 2:
The controller performs preliminary tracking of command completion status for each memory bank before polling. By maintaining knowledge of which commands have been issued and their expected completion timing, the controller can predict which banks are likely to be ready and prioritize polling those banks first.
2Productivity
If multiple memory devices are operated in parallel on a single bus, then throughput is improved, but the increased wiring impedance and capacitance limit the bus operating frequency
Solution Approach 1:
The patent segments the memory system into multiple independent channels, each with its own bus and controller. This segmentation allows parallel operation of multiple memory banks while avoiding the signal integrity issues that would arise from adding more devices to a single bus. Each channel operates independently at optimal frequency while the aggregate system achieves high throughput through parallel channel operation.
3Loss of information
If status checking is performed for every memory bank regardless of queued commands, then the controller maintains accurate status information, but processing efficiency is reduced due to unnecessary checks
Solution Approach 1:
The controller implements feedback mechanisms by tracking command completion status and using this information to guide subsequent polling decisions. The system monitors which commands have been issued to which banks and uses this feedback to determine which banks are likely to transition from busy to ready state, thereby optimizing the polling sequence and reducing unnecessary checks.
Data Source
AI summary
A memory controller and methods thereof suitable for operating a system utilizing multiple memory bus channels and/or multiple banks of memory devices on each channel wherein the memory devices is polled only when necessary. The memory controller includes means for determining a status of each individual memory device of the plurality of memory devices, a channel controller for each memory bus channel, and at least one status register on which is stored a plurality of bits. The channel controller maintains a derived status of each individual memory device based on the current and previous status data. Each individual bit of the plurality of bits of the status register corresponds to an individual memory device of the plurality of memory devices and indicates the derived status of the individual memory device which are used to determine whether to check for a queued command destined for the individual memory device.