NRZ CDR Calibration Using Run-Length Weighting
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Solution Overview
Problem
Prior art NRZ CDR units struggle with slow clock adjustments and phase/frequency offset due to noise interference, as they do not consider data dependence during transitions and fail to fully compensate channel signals, leading to incomplete compensative signals and loss-of-lock issues.
Innovation Solution
A device and method for NRZ CDR calibration using a weight calculator unit that performs run length calculations on error and data signals to generate weight data, which is then used to adjust the sampling clock signal, improving phase and frequency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the CDR unit adjusts the sampling clock signal without considering data dependence during data transition, then the device complexity is reduced, but the clock adjustment speed becomes slow and phase/frequency offset occurs
Solution Approach 1:
The patent pre-calculates weight values for different data transition patterns (0→1, 1→0, 0→0, 1→1) and stores them in a weight table before actual clock adjustment is needed. This preliminary preparation allows the CDR unit to quickly retrieve and apply appropriate weights during clock adjustments without performing complex real-time calculations, thereby improving adjustment speed while maintaining relatively simple device structure.
Solution Approach 2:
The system uses the existing data signal and error signal already present in the CDR unit to generate the weight selection signal, rather than requiring external or additional complex control mechanisms. The data transition information from the normal operation of the CDR unit is reused to drive the weight selection, making the system self-sufficient and avoiding additional complexity.
2Measurement precision
If the equalization filter fully compensates the channel signal, then the measurement precision of the compensative signal is improved, but the device complexity increases
Solution Approach 1:
Instead of attempting to perfectly equalize all frequency components of the channel signal, the patent applies partial equalization focusing on the most critical frequency ranges. The equalization filter is designed to provide sufficient compensation for the dominant channel impairments while accepting some residual distortion, thereby achieving adequate signal quality without the complexity of a full-bandwidth perfect equalizer.
3Device complexity
If the CDR unit uses traditional weight calculation without run length technique, then the device complexity is lower, but the calibration accuracy and loss-of-lock prevention capability deteriorates
Solution Approach 1:
The patent pre-calculates and stores weight values corresponding to different run length conditions and data transition patterns in a lookup table. During operation, the weight calculator unit simply retrieves the appropriate pre-computed weight based on the current data pattern and run length, avoiding complex real-time weight calculations while achieving high calibration accuracy.
Solution Approach 2:
The patent introduces run length as an additional parameter for weight selection, changing from simple data transition detection to considering both transition type and run length characteristics. This parameter expansion allows the system to adapt weights based on the temporal patterns of data sequences, improving calibration accuracy and loss-of-lock prevention while managing complexity through pre-computation.
Data Source
AI summary
The disclosure is a device and a method for Non Return to Zero (NRZ) Clock Data Recovery (CDR) calibration, which includes a CDR unit and a weight calculator unit. The CDR unit receives a compensative signal of an equalization filter to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal. The weight calculator unit receives the error signal, the transition sampling signal and the data signal, and then uses a run length technique to generate weight data. The weight data controls a voltage control oscillator (VCO) which calibrates the phase and the frequency of the sampling clock signal.