NRZI Sync Detection via Firmware Error Correction

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Solution Overview

Problem

Communication and data storage systems using NRZI encoding are susceptible to timing issues, leading to large numbers of detected errors even when the input data stream contains few actual errors, due to sync detection failures.

Innovation Solution

A hybrid system combining dedicated processing circuitry for initial sync signal detection and firmware-controlled processing for error correction, allowing the system to resolve sync signal issues that dedicated hardware alone cannot handle, by pre-processing data to correct errors and enable accurate sync detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If dedicated processing circuitry is used for sync signal detection, then processing speed is improved, but reliability deteriorates due to inability to correct errors causing sync detection failures

Engineering Contradiction:
Improveprocessing speedVSAvoidsync detection reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system divides processing into two segments: dedicated processing circuitry for initial sync signal detection and firmware-controlled processing for error correction. This segmentation allows each component to specialize in its strength while working together to achieve both speed and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The firmware performs preliminary error correction on the received data stream before the dedicated processing circuitry attempts sync signal detection. By correcting errors in advance, the system prevents sync detection failures that would otherwise require reprocessing.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If firmware-controlled processing is used for error correction, then reliability is improved, but processing speed deteriorates due to software execution overhead

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The firmware performs error correction only when the dedicated processing circuitry fails to detect the sync signal. This partial action approach applies the slower firmware processing only when necessary, maintaining overall system speed while providing reliability backup.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The dedicated processing circuitry acts as an intermediary that filters out most cases, allowing the firmware to focus only on problematic cases. This intermediary layer prevents the firmware from processing every data stream, maintaining speed while ensuring reliability for difficult cases.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If error correction is performed before sync detection, then sync detection accuracy is improved, but device complexity increases due to hybrid architecture

Engineering Contradiction:
Improvesync detection accuracyVSAvoidsystem architecture complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system merges dedicated processing circuitry and firmware-controlled processing into a unified hybrid architecture. The two components are integrated to work together seamlessly, with the firmware serving as a supplement to the hardware rather than a separate system.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8953425B1NRZI processing methods and devices to correct for sync detection failures
Publication Date: 2015.02.10 MARVELL ASIA PTE LTD
  • US8953425B1 patent drawing
  • US8953425B1 patent drawing
  • US8953425B1 patent drawing

AI summary

New and useful methods and systems for detecting sync signals/patterns in streams of data are disclosed. For example, in an embodiment system for processing data includes a first module having dedicated processing circuitry configured to detect a sync signal embedded in a received stream of data and to produce an output stream of data, and second module that includes a firmware-controlled processor configured to correct sufficient errors within the received stream of data so as to allow the first module to detect the sync signal on a condition when the first module by itself is incapable of resolving the sync signal caused by the errors in the received stream of data.