NS-SAR ADC Charge-Sharing Circuit for High-SNR Conversion
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Solution Overview
Problem
Conventional noise-shaping successive approximation analog-to-digital converters (NS-SAR ADCs) face challenges in achieving high signal-to-noise ratio (SNR) due to comparator noise and quantization noise, with passive designs requiring large comparators and additional timing slots, limiting sampling rate and power efficiency.
Innovation Solution
A noise-shaping successive approximation analog-to-digital converter using a passive noise-shaping technique with a 1-input-pair SAR comparator, incorporating a residue sampling and integration circuit with integral and residue capacitors for charge-sharing, which overlaps sampling and conversion phases without additional timing slots, eliminating the need for operational amplifiers and additional comparator input pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If passive noise-shaping design is used, then power consumption is reduced, but device area increases due to large comparator size
Solution Approach 1:
The residue voltage processing is segmented into multiple stages: sampling stage (capturing residue voltage), holding stage (maintaining voltage level), and integration stage (accumulating for noise shaping). This segmentation allows the comparator to process smaller voltage increments over multiple cycles rather than requiring large voltage handling capability in a single stage, thereby reducing comparator area while maintaining passive noise-shaping functionality.
Solution Approach 2:
The patent introduces a time dimension by using multiple timing phases (sampling phase, holding phase, integration phase) to process the residue voltage. Instead of requiring a large comparator to handle all processing simultaneously in space, the solution distributes processing across multiple time slots, allowing a smaller comparator to achieve the same noise-shaping effect through temporal multiplication.
2Measurement precision
If additional timing slots are allocated for charge-sharing procedure, then noise-shaping is achieved, but sampling rate is limited
Solution Approach 1:
The patent merges the charge-sharing procedure with the existing successive approximation conversion phases. The residue voltage sampling, holding, and integration operations are combined with the normal ADC conversion timing, allowing noise-shaping processing to occur concurrently with the main conversion function rather than requiring separate dedicated timing slots. This merging enables noise-shaping without sacrificing sampling rate.
Solution Approach 2:
The residue voltage is continuously processed throughout the conversion cycle rather than requiring discrete interruptive timing slots. The integration capacitor accumulates residue voltage continuously during the conversion process, maintaining continuous useful action for noise-shaping while the ADC performs its normal conversion function, thereby achieving both precision and high sampling rate.
3Measurement precision
If operational amplifier is used for active residue amplification, then residue amplitude is maintained, but power consumption increases
Solution Approach 1:
The patent replaces the active operational amplifier-based voltage amplification mechanism with a passive capacitive voltage division and holding mechanism. Instead of using an op amp to actively amplify and maintain residue voltage amplitude, the solution uses capacitors to passively hold and transfer voltage levels through charge conservation, eliminating the high power consumption associated with active amplification while maintaining sufficient residue amplitude for accurate processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances SNR by directly compensating noise-shaping signals on the input terminals, reducing power consumption, and increasing sampling rate through efficient charge-sharing and capacitive integration, achieving improved noise suppression without additional timing slots.
Implementation Method 1
a residue sampling and integration circuit, coupled between the DAC and the comparator, for sampling a residue voltage generated by the DAC and charge-sharing of the sampled residue voltage
Data Source
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AI summary
A noise-shaping successive approximation analog-to-digital converter (NS-SAR ADC) using a passive noise-shaping technique with 1-input-pair SAR comparator is introduced. A residue sampling and integration circuit is coupled between a DAC and the comparator, for sampling a residue voltage generated by the DAC and charge-sharing of the sampled residue voltage. A first integral capacitor is coupled between a first input terminal of a comparator and a first output terminal of a DAC. After a first residue capacitor samples a residue generated by the DAC, the first residue capacitor is coupled to the first integral capacitor for charge-sharing of the residue voltage.