NSDL for System-on-Chip JTAG Testing
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Solution Overview
Problem
Current hardware description languages, such as BSDUHSDL, are inadequate for describing complex dynamic scan chains and test procedures required for chip-level JTAG testing, particularly in the transition from board-level to chip-level testing, and fail to provide sufficient space for describing test procedures for each component of the system.
Innovation Solution
A new hardware description language, New BSDL (NSDL), is introduced to facilitate chip-level JTAG testing by providing a bottom-up approach that supports algorithmic descriptions of system-on-chip components and their interconnections, enabling the generation of algorithmic descriptions for the entire system or its portions, and allowing for dynamic modification of the scan path through the use of crossroad devices and parallel access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If BSDUHSDL is used for board-level JTAG testing, then testing of printed circuit boards is enabled, but the language becomes inadequate for chip-level JTAG testing and cannot describe complex dynamic scan chains
Solution Approach 1:
The patent segments the boundary scan register into multiple independent scan chains, allowing separate description and control of each chain. This segmentation enables the language to handle complex dynamic scan chains at chip-level by breaking down the overall scanning function into manageable, independently describable units, thus resolving the limitation of BSDUHSDL which treats the boundary scan register as a single ordered list.
Solution Approach 2:
The patent introduces dynamic scan chain configuration capabilities that allow the scan path to be reconfigured during testing operations. This dynamic feature enables adaptation to different chip-level testing scenarios by modifying scan chain connections and configurations on-the-fly, making the description language versatile enough for chip-level JTAG while maintaining structured organization through the enhanced language syntax.
2Ease of operation
If BSDUHSDL uses an ordered list of cells for boundary scan register, then board-level testing is simplified, but it fails to provide space for describing test procedures for each component
Solution Approach 1:
The patent implements a nested hierarchical structure where component-specific test procedures are embedded within the overall boundary scan register description. Each component can have its own nested test procedure definitions that are integrated into the global scan chain configuration. This nesting allows preservation of component-specific test information while maintaining the organized structure needed for ease of operation, effectively resolving the limitation of BSDUHSDL which lacks space for detailed component-level test procedures.
3Adaptability or versatility
If static description of boundary scan register is used, then implementation is simple, but it cannot describe complex dynamic scan chains required in IJTAG
Solution Approach 1:
The patent transforms the static boundary scan register description into a dynamic model where scan chains can be reconfigured based on testing requirements. The enhanced language includes constructs for defining conditional connections, reconfigurable scan paths, and dynamic cell selection. This dynamic capability enables description of complex scan chains required in IJTAG while the language maintains reasonable structure through systematic syntax rules, thus achieving adaptability without excessive complexity.
Data Source
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AI summary
The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system- on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system- on-chip.