NSFET Source/Drain Doping for Lower Resistance at Scaled Nodes
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in reducing electrical resistance and improving carrier mobility in nanostructure field-effect transistors (NSFETs), which affect their electrical performance.
Innovation Solution
An ion implantation process is used to dope end portions of semiconductor material layers in NSFETs, forming doped regions with higher carrier mobility and lower electrical resistance by implanting a dopant into exposed regions of the semiconductor material, followed by an anneal process to activate the dopant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but electrical resistance increases and carrier mobility decreases
Solution Approach 1:
The patent applies local quality by creating doped regions with different electrical properties at specific locations within the semiconductor structure. By selectively doping end portions of semiconductor layers with different dopant types and concentrations, the invention optimizes carrier mobility and reduces electrical resistance in critical regions while maintaining the overall miniaturized structure for high integration density.
Solution Approach 2:
The patent utilizes parameter changes by varying dopant concentration, dopant type, and doping depth in different regions of the semiconductor structure. Through controlled ion implantation processes with different energies and doses, the invention creates graded doping profiles that adjust electrical parameters to optimize both electrical performance and integration density at scaled dimensions.
2Productivity
If feature size is reduced to improve integration density, then manufacturing capacity increases, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The patent applies preliminary action by performing ion implantation doping before certain subsequent processing steps. By doping end portions of semiconductor layers at defined stages in the fabrication sequence, the invention ensures precise dopant placement and activation before structural formation, thereby achieving the required manufacturing precision even at reduced feature sizes.
Solution Approach 2:
The patent replaces traditional thermal diffusion methods with ion implantation technology. This substitution enables precise control over dopant depth, concentration, and distribution through controlled ion beam parameters, achieving superior manufacturing precision compared to conventional thermal processes, especially at scaled dimensions where thermal diffusion becomes less controllable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces electrical resistance and improves the electrical performance of NSFETs by creating doped regions with increased carrier mobility, enhancing the device's operational efficiency.
Implementation Method 1
an ion implantation process is performed to implant a dopant into end portions of layers of a semiconductor material
Implementation Method 2
followed by an anneal process to activate the dopant
Data Source
AI summary
A method of forming a semiconductor device includes: forming a fin structure that protrudes above a substrate, where the fin structure includes a fin and a layer stack overlying the fin, where the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a gate structure over the fin structure; forming source/drain openings in the fin structure on opposing sides of the gate structure; replacing first end portions of the first semiconductor material exposed by the source/drain openings with inner spacers; after the replacing, performing an ion implantation process, where the ion implantation process implants a first dopant into second end portions of the second semiconductor material exposed by the source/drain openings; and after performing the ion implantation process, forming source/drain regions in the source/drain openings.