NSFET Gate Cut Layout to Prevent Photoresist Bowing
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing minimum feature sizes, leading to issues such as photoresist peeling and bowing during the fabrication of nanostructure field-effect transistor (NSFET) devices, which can cause device failure and reduce production yield.
Innovation Solution
The location of the cut pattern in the photoresist layer is shifted away from the center axis of the gate structure, and an anisotropic etching process with low etching selectivity is used to form openings, reducing scattered ions/radicals and minimizing asymmetric etching effects to avoid bowing, thereby improving device formation and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but photoresist peeling and bowing issues arise during fabrication
Solution Approach 1:
The patent applies asymmetry by intentionally shifting the cut pattern location away from the center axis of the gate structure. This asymmetric positioning of the opening relative to the gate structure prevents symmetric bowing during etching, thereby resolving the technical contradiction by enabling reduced feature sizes without suffering from photoresist peeling and bowing issues that would compromise fabrication reliability
2Ease of manufacture
If conventional etching processes are used to form openings, then the fabrication process is simple, but scattered ions/radicals cause asymmetric etching effects and bowing
Solution Approach 1:
The patent applies preliminary anti-action by using an anisotropic etching process with low etching selectivity that reduces scattered ions and radicals before they can cause asymmetric etching effects. This preliminary control of the etching environment prevents bowing and maintains manufacturing precision while keeping the fabrication process relatively simple
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces device failure and enhances production yield by addressing photoresist peeling and bowing issues, ensuring consistent and reliable fabrication of NSFET devices.
Implementation Method 1
an anisotropic etching process with low etching selectivity is used to form openings
Implementation Method 2
an anisotropic etching process with low etching selectivity is used to form openings, reducing scattered ions/radicals
Data Source
AI summary
A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming an interlayer dielectric (ILD) layer over the fin around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the fin to cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, where an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first and the second dielectric plugs; etching, using the patterned mask layer as an etching mask, the segment of the gate structure to form a recess in the gate structure; extending the recess into the fin by performing an anisotropic etching process to deepen the recess; and after extending the recess, filling the recess with a dielectric material.