NSFET Gate Isolation Layout for Reduced Transistor Spacing
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Solution Overview
Problem
Existing methods for forming semiconductor devices with nanostructure field-effect transistors (NSFETs) struggle to maintain precise control over the formation of separate metal gates as feature sizes continue to scale down, leading to electrical shorts and reduced production yield due to poor overlay control and unintentional removal of metal layers.
Innovation Solution
A method involving the formation of dielectric structures over dielectric fins to create etching windows with increased width and alignment, using dielectric structures as retaining walls to selectively remove conductive structures, allowing for self-aligned dielectric layer formation and reduced spacing between NSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are reduced to increase integration density, then more electronic components can be integrated into a given area, but manufacturing precision deteriorates leading to poor overlay control and unintentional removal of metal layers
Solution Approach 1:
The method performs preliminary patterning of the metal layer using a first patterned masking layer before forming the second patterned masking layer. This preliminary action establishes a foundation that guides subsequent processing steps, ensuring that metal gates are formed with proper spacing and alignment even as feature sizes reduce. The first patterned masking layer is formed with wider spacing that is easier to control, and subsequent steps use this as a reference for precise metal gate formation.
Solution Approach 2:
The patent segments the gate formation process into multiple distinct stages: first forming a continuous metal layer, then selectively removing portions using sequentially formed patterned masking layers. This segmentation allows each step to be optimized independently - the first masking layer for broader alignment tolerance, and the second for precise gate definition - thereby maintaining manufacturing precision while achieving reduced spacing.
2Quantity of substance
If spacing between NSFETs is reduced to increase integration density, then more transistors fit in a given area, but electrical shorts occur due to poor overlay control
Solution Approach 1:
The method removes portions of the metal layer in preliminary steps before final gate formation. By selectively removing metal in controlled stages using patterned masking layers, the process ensures that metal gates are properly isolated from each other before subsequent processing, preventing electrical shorts while achieving reduced spacing between NSFETs.
Solution Approach 2:
Dielectric structures are formed over fins before metal gate formation to serve as retaining walls. These preliminary dielectric structures prevent metal layer removal in unwanted areas and ensure proper spacing between metal gates, thereby preventing electrical shorts while enabling reduced NSFET spacing.
3Ease of manufacture
If conventional metal gate formation methods are used, then process simplicity is maintained, but production yield reduces due to unintentional removal of metal layers
Solution Approach 1:
The method forms dielectric structures over fins before forming metal gates. These preliminary dielectric structures act as retaining walls that protect underlying metal layers during subsequent etching and processing steps, preventing unintentional metal layer removal and improving production yield while maintaining a systematic manufacturing process.
Solution Approach 2:
Patterned masking layers serve as intermediary elements between the etching process and the metal layer. These masking layers are selectively formed and removed in controlled steps, mediating the interaction between etching chemistry and metal structures to prevent unwanted metal removal while enabling precise gate formation.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.