NSFET Gate Recess Etching for Symmetric Backside Via Openings
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of asymmetric sidewall profiles in semiconductor device manufacturing, particularly in nanostructure field-effect transistors (NSFETs), leads to issues with the formation of backside vias in backside power rail applications, causing device failure and reduced production yield.
Innovation Solution
An isotropic etching process is used to completely remove the segment of the gate structure underlying the cut pattern, followed by an anisotropic etching process to form the opening, ensuring a symmetric sidewall profile and avoiding photoresist peeling issues, thereby facilitating the formation of backside vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If anisotropic etching process is used to form the opening, then the etching speed and directionality are improved, but the sidewall profile becomes asymmetric causing device failure
Solution Approach 1:
The patent applies preliminary action by first performing an isotropic etching process to remove the gate structure segment before performing the anisotropic etching to form the opening. This preliminary removal of the gate structure eliminates the cause of asymmetric scattering, allowing the subsequent anisotropic etching to produce symmetric sidewalls while maintaining high etching speed.
2Device complexity
If the gate structure segment is not completely removed, then the manufacturing process is simplified, but asymmetric scattering of etchant occurs causing photoresist peeling and device failure
Solution Approach 1:
The patent uses preliminary action by completely removing the gate structure segment through isotropic etching before forming the opening. This preliminary removal prevents asymmetric scattering of etchant during subsequent anisotropic etching, eliminating photoresist peeling and ensuring device reliability.
Solution Approach 2:
The patent applies parameter changes by switching from anisotropic etching to isotropic etching for the specific step of removing the gate structure segment. This change in etching mode (from directional to uniform) ensures complete removal of the gate structure without leaving residues that would cause asymmetric scattering, thereby preventing device failure.
3Manufacturing precision
If isotropic etching is used to remove the gate structure segment, then symmetric sidewall profile is achieved, but the etching process time increases
Solution Approach 1:
The patent applies segmentation by dividing the etching process into two distinct stages: first, isotropic etching to remove the gate structure segment, and second, anisotropic etching to form the opening with symmetric sidewalls. This segmentation allows each process to be optimized independently, achieving symmetric profiles while managing overall process time efficiently.
Solution Approach 2:
The patent uses partial action by applying isotropic etching only to the specific region where the gate structure segment exists, rather than performing isotropic etching throughout the entire opening formation process. This targeted approach achieves the necessary symmetric sidewall profile while minimizing the time penalty associated with isotropic etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures a symmetric sidewall profile for the opening, preventing obstruction of backside vias and enhancing device reliability and production yield by avoiding asymmetric etching effects.
Implementation Method 1
An isotropic etching process is used to completely remove the segment of the gate structure underlying the cut pattern
Implementation Method 2
followed by an anisotropic etching process to form the opening, ensuring a symmetric sidewall profile
Data Source
AI summary
A method of forming a semiconductor device includes: forming a gate structure over a fin; forming an interlayer dielectric (ILD) layer over the fin around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the fin, where the first and second dielectric plugs cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, where an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first and second dielectric plugs; etching, using the patterned mask layer as an etching mask, the segment of the gate structure using an isotropic etching process to form a recess in the gate structure; extending the recess into the fin by performing an anisotropic etching process; and after extending the recess, filling the recess with a dielectric material.