NSFET Gate Separation Using Dielectric Fins and Etch Windows
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Solution Overview
Problem
As minimum feature sizes in semiconductor devices continue to scale down, existing methods for forming separate metal gates in nanostructure field-effect transistors (NSFETs) lack sufficient control, leading to electrical shorts and reduced production yield due to poor overlay control and unintentional removal of metal layers.
Innovation Solution
A method involving the formation of dielectric structures over dielectric fins to create etching windows with increased width and shifted locations, using these structures as retaining walls to selectively remove conductive layers and prevent unintentional removal of metal gates, thereby ensuring precise formation of separate metal gates with reduced spacing between NSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing methods are used to form separate metal gates in NSFETs, then the process is simpler, but overlay control is poor and unintentional removal of metal layers occurs
Solution Approach 1:
The patent segments the gate formation process into multiple distinct steps: forming mandrels, depositing first metal layer, forming openings, depositing dielectric layer, forming second openings, and depositing second metal layer. Each step is carefully controlled to prevent overlay errors and unintentional metal layer removal, thereby improving manufacturing precision at the cost of increased process complexity
Solution Approach 2:
The patent performs preliminary actions by first forming mandrels and depositing the first metal layer before creating openings. The dielectric layer is deposited and planarized before forming the second openings. These preliminary steps establish a controlled foundation that enables precise overlay control in subsequent steps, preventing unintentional metal layer removal
2Productivity
If spacing between NSFETs is reduced to increase integration density, then more devices fit in given area, but electrical shorts increase due to poor overlay control
Solution Approach 1:
The patent introduces dielectric layers as intermediary materials between adjacent metal gates and NSFET structures. These dielectric layers act as insulation barriers that prevent electrical shorts between closely spaced devices. The intermediary dielectric structures enable reduced spacing between NSFETs while maintaining reliability by providing electrical isolation
Solution Approach 2:
The patent employs self-aligned processes where previously formed structures serve as alignment references for subsequent steps. The mandrels and metal layers formed in earlier steps automatically provide alignment guidance for opening formation and dielectric deposition, ensuring precise spacing control and preventing electrical shorts without requiring additional alignment steps
3Productivity
If multi-gate FET scaling is continued to improve device performance, then production yield increases, but fabrication control becomes more difficult at 3nm node
Solution Approach 1:
The patent segments the gate formation into multiple controlled deposition and etching steps rather than attempting to form all metal gates in a single process. This segmentation allows each step to be optimized and controlled independently, maintaining fabrication control even at the challenging 3nm technology node while continuing to scale for improved production yield
Solution Approach 2:
The patent transitions from planar gate formation to three-dimensional multi-gate structures by forming metal layers that wrap around nanostructures in multiple dimensions. This dimensional transition enables continued scaling and improved device performance while the step-by-step formation process maintains fabrication control through self-alignment and intermediate dielectric layers
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.