NSFET Nanostructure Reshaping for Gate Dielectric Formation
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Solution Overview
Problem
As semiconductor feature sizes continue to shrink, it becomes challenging to integrate more components into a given area while maintaining control over the channel regions of nanostructure field-effect transistors (NSFETs), as the distance between adjacent nanostructures becomes too small to form gate dielectric layers effectively, and the thickness of channel regions makes it difficult to control the on/off switching of the device.
Innovation Solution
A method is developed to reshape the nanostructures by performing a selective etching process, thinning the middle portions while keeping the end portions unchanged, resulting in a dumbbell-shaped cross-section, which increases the distance between nanostructures and reduces their thickness, facilitating easier gate dielectric formation and improved control over the NSFET device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but the distance between adjacent nanostructures becomes too small to form gate dielectric layers effectively
Solution Approach 1:
The patent segments the originally continuous channel region into multiple discrete nanostructures (nanosheets or nanowires) separated by dielectric material. This segmentation allows gate dielectric layers to be formed between the separated structures, solving the problem of insufficient spacing that occurs when continuously reducing feature sizes for higher integration density.
Solution Approach 2:
The patent transitions from planar 2D channel structures to vertically stacked 3D nanostructures. By stacking multiple nanostructures vertically, the patent achieves higher integration density in the vertical dimension while maintaining adequate horizontal spacing for gate dielectric layer formation, thus resolving the contradiction between density and manufacturability.
2Ease of operation
If channel region thickness is reduced to improve device control, then on/off switching control is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent applies different material compositions to different parts of the channel structure. The channel regions are formed with specific semiconductor materials (e.g., SiGe and Si layers) that have different properties, allowing local optimization of both control characteristics and manufacturing feasibility. The varied composition enables precise thickness control through selective etching processes.
Solution Approach 2:
The patent changes material parameters by using alternating layers of different semiconductor materials with distinct etch rates and crystalline structures. This parameter variation enables precise control of the final channel thickness through selective removal processes, making it easier to achieve target dimensions while maintaining manufacturing precision.
3Ease of manufacture
If selective etching is performed to reshape channel regions, then gate dielectric layer formation is facilitated, but process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the multi-layer semiconductor structure with alternating materials before the final channel definition step. This preliminary structuring with etch-stop layers and sacrificial materials enables subsequent selective removal processes to automatically create the desired channel shapes, simplifying the overall process despite the multiple steps involved.
Solution Approach 2:
The patent introduces intermediary sacrificial layers and etch-stop layers between the semiconductor layers. These intermediary structures facilitate the selective etching process by providing clear differentiation points, allowing precise channel region definition while making the complex multi-step etching process more controllable and manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reshaping process enhances the ability to form gate dielectric layers around the nanostructures, increases manufacturing yield, and improves control over the NSFET device's on/off switching by reducing the thickness of channel regions and increasing the distance between them.
Implementation Method 1
performing a selective etching process, thinning the middle portions while keeping the end portions unchanged
Data Source
AI summary
A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.