NSFET Gate Segment Recess Etching to Prevent Opening Bowing
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Solution Overview
Problem
The challenges of photoresist peeling and bowing issues during the fabrication of nanostructure field-effect transistor (NSFET) devices, particularly in CMODE and CPODE processes, which affect the integration density and production yield.
Innovation Solution
The location of the cut pattern in the photoresist layer is intentionally shifted away from the center axis of the gate structure, combined with an anisotropic etching process of lower selectivity to form openings, reducing scattered ions/radicals and asymmetric etching effects, thereby avoiding bowing and improving device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the cut pattern is positioned at the center axis of the gate structure, then the etching process is simpler, but photoresist peeling and bowing issues occur during fabrication
Solution Approach 1:
The patent applies asymmetry by intentionally offsetting the cut pattern from the center axis of the gate structure. This asymmetric positioning prevents photoresist peeling and bowing issues that occur with symmetric center-aligned patterns, thereby improving manufacturing precision while maintaining etching process simplicity
Solution Approach 2:
The patent employs preliminary anti-action by pre-positioning the cut pattern offset from the center axis before the etching process begins. This preliminary adjustment counteracts the potential for photoresist peeling and bowing that would otherwise occur during etching, preventing defects before they can manifest
2Manufacturing precision
If higher selectivity etching is used to improve precision, then etching control is better, but scattered ions/radicals cause asymmetric etching and bowing
Solution Approach 1:
The patent uses asymmetry in pattern positioning to counterbalance the asymmetric etching effects caused by scattered ions and radicals. By offsetting the cut pattern from the center, the resulting asymmetric etching produces a symmetric final opening profile, maintaining both precision and reliability
Solution Approach 2:
The patent converts the harmful effect of scattered ions and radicals causing asymmetric etching into a benefit. By intentionally positioning the cut pattern asymmetrically, the harmful asymmetric etching produces the desired symmetric opening profile, transforming a defect mechanism into a solution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces device failure and enhances production yield by preventing bowing in the openings, ensuring precise feature dimensions and reliable connection to backside power rails.
Implementation Method 1
an anisotropic etching process with lower etching selectivity to form the opening
Implementation Method 2
anisotropic etching process with lower etching selectivity to form the opening
Data Source
AI summary
A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming an interlayer dielectric (ILD) layer over the fin around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the fin to cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, where an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first and the second dielectric plugs; etching, using the patterned mask layer as an etching mask, the segment of the gate structure to form a recess in the gate structure; extending the recess into the fin by performing an anisotropic etching process to deepen the recess; and after extending the recess, filling the recess with a dielectric material.