NSFET Source/Drain Isolation Structure for Leakage Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices undergo miniaturization, they face challenges with substrate leakage and well isolation leakage, which increase with shrinking feature sizes, affecting device performance.

Innovation Solution

A dielectric layer is formed under the source/drain regions in nanostructure field-effect transistor (NSFET) devices to physically and electrically isolate the source/drain regions from the underlying fins, reducing substrate and well isolation leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but substrate leakage and well isolation leakage increase

Engineering Contradiction:
Improveintegration densityVSAvoidsubstrate leakage and well isolation leakage
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

A dielectric layer is introduced as an intermediary between the source/drain regions and the substrate/fins. This dielectric layer acts as a mediator that blocks the leakage current paths while allowing the source/drain regions to maintain their electrical function. The dielectric material is positioned specifically at the interface where leakage occurs, providing targeted isolation without affecting the overall device operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric layer is applied locally only where needed - specifically under the source/drain regions - rather than uniformly across the entire device. This localized approach provides effective leakage blocking at the critical interface while minimizing the impact on device performance and maintaining the miniaturized structure. The selective placement allows the device to benefit from improved isolation without the penalties of comprehensive dielectric coverage.

Inventive Principle:
Principle #3Local quality

2Object-generated harmful factors

If source/drain regions are isolated from underlying fins by a dielectric layer, then substrate and well isolation leakage are reduced, but device structure complexity increases

Engineering Contradiction:
Improvesubstrate and well isolation leakageVSAvoiddevice structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The device structure is segmented into distinct functional regions by introducing the dielectric layer as a separate component. This segmentation divides the source/drain region from the underlying fin structure, creating clearly defined zones with specific functions. The dielectric layer itself becomes a distinct segment that performs the isolation function, allowing for modular design and easier manufacturing control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dielectric layer serves as an intermediary element that simplifies the overall device architecture by providing a clear separation between the source/drain regions and the fin structure. Rather than attempting to achieve isolation through complex doping profiles or intricate geometric arrangements, the intermediary dielectric layer provides a straightforward, manufacturable solution that reduces leakage while maintaining structural clarity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dielectric layer effectively prevents or reduces substrate and well isolation leakage, thereby enhancing the performance of NSFET devices by improving electrical isolation and reducing leakage currents.

Implementation Method 1

A dielectric layer is formed under the source/drain regions in nanostructure field-effect transistor (NSFET) devices to physically and electrically isolate the source/drain regions from the underlying fins

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS20240379750A1Nanostructure Field-Effect Transistor Device and Method of Forming
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379750A1 patent drawing
  • US20240379750A1 patent drawing
  • US20240379750A1 patent drawing

AI summary

A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.