NSP Manager Memory Segmentation for Packet Classification

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Solution Overview

Problem

Current packet classification methods face inefficiencies due to the exponential growth in network bandwidth and complexity of network applications, with existing algorithms trading memory for time and relying on resource-intensive hardware like TCAMs, which are inflexible and power-consuming.

Innovation Solution

A method and system for managing a database using a tree structure and multiple cluster memories with optimized packing and replication strategies to minimize memory access, enabling efficient packet classification across multiple banks and ports, allowing for intelligent handling of diverse rule sets without significant performance loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If TCAMs are used for packet classification, then classification speed is improved, but power consumption and hardware complexity increase

Engineering Contradiction:
Improveclassification speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent divides the packet classification database into multiple cluster memories, each containing specific buckets and rules. This segmentation allows parallel access to different portions of the classification data, maintaining high speed while using standard memory technologies with lower power consumption compared to monolithic TCAM solutions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates replicated copies of rule sets across multiple memory banks and clusters. By distributing identical or complementary rule copies across different memory locations, the system enables parallel lookup operations that achieve TCAM-like speed using conventional memory, reducing overall power consumption.

Inventive Principle:
Principle #26Copying

2Speed

If TCAMs are used for packet classification, then classification speed is improved, but device complexity increases

Engineering Contradiction:
Improveclassification speedVSAvoidhardware complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The classification database is segmented into multiple manageable cluster memories with specific buckets and rules. Each cluster can be independently managed and accessed, simplifying the overall system architecture compared to a single complex TCAM while maintaining high classification speed through parallel access mechanisms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses universal memory structures and access protocols that can handle diverse rule sets and classification requirements. The same memory architecture supports various packet classification scenarios, reducing hardware complexity by avoiding specialized components for each specific classification task.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If memory is increased to store more rules, then classification accuracy is improved, but memory access time increases

Engineering Contradiction:
Improveclassification accuracyVSAvoidmemory access time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent organizes the expanded rule database into multiple cluster memories with specific buckets, allowing the system to store comprehensive classification rules while accessing only relevant portions during lookup. This segmentation prevents the need to scan entire memory spaces, maintaining fast access times despite increased storage capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical memory organization with multiple dimensions including clusters, banks, and buckets. This multi-dimensional structure allows efficient navigation to specific rule sets, reducing access time by avoiding linear search through the entire rule database while maintaining high classification accuracy through complete rule coverage.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Reliability

If more cluster memories are accessed during tree walking, then rule coverage is improved, but access conflicts increase

Engineering Contradiction:
Improverule coverageVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent assigns specific buckets and rules to specific cluster memories based on local requirements and access patterns. This local optimization ensures that each cluster memory contains the most relevant rules for its designated function, improving rule coverage while minimizing access conflicts by reducing overlap in memory access patterns.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent performs preliminary organization of rules and buckets into appropriate cluster memories before classification operations begin. This pre-arrangement optimizes the distribution of rules across clusters to minimize access conflicts during tree walking, ensuring comprehensive rule coverage is achieved without sacrificing processing efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10229144B2NSP manager
Publication Date: 2019.03.12 MARVELL ASIA PTE LTD
  • US10229144B2 patent drawing
  • US10229144B2 patent drawing
  • US10229144B2 patent drawing

AI summary

In an embodiment, a method of updating a memory with a plurality of memory lines, the memory storing a tree, a plurality of buckets, and a plurality of rules, can include maintaining a copy of the memory with a plurality of memory lines. The method can further include writing a plurality of changes to at least one of the tree, the plurality of buckets, and the plurality of rules to the copy. The method can additionally include determining whether each of the plurality of changes is an independent write or a dependent write. The method can further include merging independent writes to the same line of the copy. The method further includes transferring updates from the plurality of lines of the copy to the plurality of lines of the memory.