Voltage-Stacked NTC Chips Inter-Chip IO via Internal Voltage Shift
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Solution Overview
Problem
In voltage stacked near threshold computing systems, the lack of overlap between supply voltages of chips hinders inter-chip communication using standard IOs and simple wires, as NTC chips operate at 0.4V, while other chips require higher voltages like 1.8V, 1.5V, or 1.2V for communication.
Innovation Solution
A system where near threshold computing chips are stacked with a primary supply voltage and two secondary supply voltages higher than the primary, along with primary and secondary ground nodes, generating two internal voltage versions with a set voltage shift, allowing standard IO functions and inter-chip communication via data lines, and optionally using charge pumps to boost voltages for LVCMOS standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If NTC chips operate at 0.4V supply voltage for minimum-energy computation, then energy efficiency is improved, but inter-chip communication capability deteriorates due to voltage mismatch with standard IO devices
Solution Approach 1:
The power delivery network is segmented into multiple voltage domains (0.4V for NTC computation, 1.2V/1.8V for standard IO communication). Each chip in the stack operates in its optimal voltage domain while voltage conversion circuits enable communication between domains, resolving the contradiction between energy efficiency and communication capability.
Solution Approach 2:
Voltage conversion circuits act as intermediaries between the 0.4V NTC chips and 1.2V/1.8V standard IO devices. These intermediary components enable voltage-matched communication while allowing NTC chips to maintain their low-voltage operation for energy efficiency.
2Adaptability or versatility
If higher supply voltage is used to enable standard IO communication, then inter-chip communication capability is improved, but power delivery efficiency deteriorates
Solution Approach 1:
Different regions of the stacked chip system operate at different voltages optimized for their specific functions: 0.4V for computation-critical NTC chips to minimize energy loss, and 1.2V/1.8V for IO-critical interfaces to ensure communication capability. This local optimization resolves the contradiction between communication capability and power efficiency.
3Loss of energy
If NTC chips are arranged in stacked fashion for power delivery, then power delivery efficiency is improved, but inter-chip communication complexity increases due to voltage mismatch
Solution Approach 1:
The voltage conversion infrastructure serves multiple functions: it enables communication between different voltage domains, provides voltage matching for standard IO interfaces, and maintains backward compatibility with existing communication protocols. This multi-functionality reduces overall system complexity despite the stacked architecture.
4Adaptability or versatility
If standard IO devices operating at 1.2V/1.8V are used for inter-chip communication, then communication protocol compatibility is improved, but voltage overlap with NTC chips deteriorates
Solution Approach 1:
The system transitions from a single-voltage-plane architecture to a multi-voltage-stack architecture where communication occurs across voltage dimensions. Each chip layer operates at its optimal voltage while voltage conversion bridges connect different voltage layers, enabling protocol compatibility without requiring voltage overlap.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective inter-chip communication within the stack and with other chips using standard IOs, facilitating compute tasks by generating internal voltages that overlap and support 1.2V LVCMOS standards, enhancing power delivery efficiency.
Implementation Method 1
each of the near threshold computing chips further comprises one or more charge pumps electrically coupled to one or more input-output components, wherein the one or more charge pumps are configured to boost the two versions of the internal voltage to a higher voltage for communication between the near threshold computing chips within the stack
Data Source
AI summary
A voltage stacked system that includes a stack of near threshold computing (NTC) chips for achieving inter-chip communication with simple wires as interconnections is disclosed. The chips include at least two secondary supply voltages and at least a secondary ground voltage electrically coupled to the stack of the chips arranged in series. The secondary supply and ground voltages are tapped in a predefined sequence at one or more predefined access points in the stack to generate two versions of an internal voltage within each of the chips. Each of the two versions of the internal voltage is a voltage difference between respective supply voltages and ground voltages, and the two have a set voltage shift such that the chips in the stack have supply voltages overlapping with those in the neighboring chips. Optionally, the two voltages are boosted to further higher voltages as needed using charge pumps.