NTP Clock Synchronization for VoIP Gateways

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Solution Overview

Problem

Conventional methods for transmitting voice and voice band data over packet-based networks, such as VoIP, face challenges with clock drift compensation, requiring separate estimators, resamplers, and additional processing power, which can introduce noise and distortion, especially in high-bandwidth applications like V.90 and V.92 modems.

Innovation Solution

The system synchronizes local clocks at each node using the Network Time Protocol (NTP), eliminating the need for clock drift compensation by providing a common time reference, thereby ensuring accurate and noise-free transmission of time-sensitive data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate clock drift estimators and resamplers are used for each voice channel, then clock drift compensation is achieved, but device complexity increases

Engineering Contradiction:
Improveclock drift compensationVSAvoidseparate estimators and resamplers per channel
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the clock drift compensation function into a single common clock source that serves all voice channels simultaneously. Instead of having separate estimators and resamplers for each channel, a single phase-locked loop (PLL) circuit generates a common clock signal that is distributed to all channels, thereby reducing device complexity while maintaining reliable clock drift compensation across all voice channels.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The common clock source generated by the PLL circuit serves multiple functions: it provides timing synchronization for all voice channels, compensates for clock drift across the entire system, and eliminates the need for channel-specific compensation mechanisms. This multi-functional approach resolves the contradiction by achieving reliable clock drift compensation without increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If resampling is used to compensate for clock drift, then clock synchronization is improved, but signal distortion increases

Engineering Contradiction:
Improveclock synchronizationVSAvoidsignal distortion
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent replaces the software-based resampling mechanism with a hardware-based phase-locked loop (PLL) circuit that generates a common clock signal. This hardware approach provides precise clock synchronization through analog phase and frequency detection, eliminating the need for digital resampling operations that introduce signal distortion. The PLL circuit achieves accurate clock synchronization while preserving signal integrity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If resampling is performed to compensate for clock drift, then clock rate differences are corrected, but processing power requirements increase

Engineering Contradiction:
Improveclock rate correctionVSAvoidCPU processing power
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent replaces CPU-based software resampling with a dedicated hardware PLL circuit that performs clock rate correction in the analog domain. The PLL circuit continuously adjusts the phase and frequency of the common clock signal to match the network clock rate, providing reliable clock rate correction without consuming CPU processing power. This hardware implementation offloads the clock synchronization function from the general-purpose processor.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

4Measurement precision

If jitter buffer is used for clock drift estimation, then drift measurement is achieved, but buffer space for jitter compensation is reduced

Engineering Contradiction:
Improveclock drift measurementVSAvoidjitter buffer space
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent extracts the clock drift compensation function from the jitter buffer mechanism and implements it through a separate common clock source generated by a PLL circuit. The jitter buffer is dedicated solely to jitter compensation, while the PLL circuit independently handles clock drift compensation by generating a common clock signal synchronized to the network clock rate. This separation eliminates the need to reserve jitter buffer space for drift estimation.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS7602815B2Using network time protocol in voice over packet transmission
Publication Date: 2009.10.13 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US7602815B2 patent drawing
  • US7602815B2 patent drawing
  • US7602815B2 patent drawing

AI summary

One or more methods and systems of effectively transmitting voice and voice band data from one node to another are presented. In one embodiment, the system comprises an NTP time server generating absolute times to computing devices such as residential voice over internet protocol (VoIP) gateways. The NTP time server generates absolute times in response to NTP time requests made by one or more computing devices such as residential VoIP gateways. In one embodiment, the method comprises determining an adequate rate for requesting absolute times from an NTP server, making periodic requests to the NTP server, obtaining the absolute times from the NTP server, and generating an adjustment parameter for use by a computing device such as a residential VoIP gateway.