Selective Amorphization for N-Transistor Threshold Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for forming multiple N-type semiconductor devices with different threshold voltage levels are time-consuming and expensive, particularly when employing stress memorization techniques (SMT) in combination with threshold voltage adjusting ion implantation processes, which can increase junction leakage currents and complicate the manufacturing process.
Innovation Solution
A method involving a common threshold voltage adjusting ion implantation process followed by selective amorphization and re-crystallization processes, using a capping material layer with a high Young's modulus to create different threshold voltage levels in N-type transistors without degrading high-voltage devices, thereby reducing the complexity and cost of the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stress memorization techniques (SMT) are employed to improve device performance, then electron mobility increases, but junction leakage currents increase and manufacturing complexity increases
Solution Approach 1:
The patent applies SMT selectively only to low-voltage N-type devices that require high performance, while excluding high-voltage devices from the amorphization implant process. This is achieved through selective masking that exposes only the active regions of low-voltage devices during the implant process, thereby improving electron mobility where needed without increasing junction leakage in high-voltage devices.
Solution Approach 2:
The patent modifies the implantation parameters by using a reduced fluence (dose) of amorphizing ions compared to conventional SMT processes. This reduced fluence, combined with selective application, provides sufficient stress to improve electron mobility in low-voltage devices while minimizing the creation of stacking faults and junction leakage in high-voltage devices.
2Manufacturing precision
If multiple ion implantation processes are used to form devices with different threshold voltages, then threshold voltage control improves, but manufacturing time and cost increase
Solution Approach 1:
The patent combines the threshold voltage adjustment implant and the SMT amorphization implant into a single unified ion implantation process. By using a reduced fluence of amorphizing ions and selective masking, the process achieves both threshold voltage control and stress memorization effects in one step, eliminating the need for separate implantation processes and reducing manufacturing time and cost.
Solution Approach 2:
The ion implantation process is designed to serve multiple functions simultaneously: it adjusts threshold voltage for both low-voltage and high-voltage devices, and selectively applies stress memorization to low-voltage devices. This multi-functional approach consolidates what would traditionally require multiple separate processes into a single universal implantation step.
3Speed
If channel length is decreased to improve switching speed, then operating speed increases, but short channel effects worsen
Solution Approach 1:
The patent changes the physical state of the source/drain regions by creating amorphous silicon through ion implantation, which then crystallizes during annealing. This phase change process, combined with the volume shrinkage upon crystallization, generates compressive stress in the channel region that improves carrier mobility and compensates for short channel effects, allowing continued scaling without sacrificing device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient formation of N-type transistors with distinct threshold voltage levels, reducing junction leakage currents and maintaining low power consumption in high-voltage devices, while simplifying the manufacturing process and reducing costs.
Implementation Method 1
stress memorization techniques (SMT) wherein certain types of stresses are induced in the channel region of the device. More specifically, SMT techniques are used to create a tensile stress in the channel region for N-type transistors (to increase electron mobility)
Implementation Method 2
performing an amorphization implant process on the source/drain regions of the exposed N-type transistors
Implementation Method 3
performing a brief re-crystallization anneal process (e.g., 650° C. for about 10 minutes in a nitrogen ambient)
Implementation Method 4
performing a common threshold voltage adjusting ion implantation process on the first and second active regions
Data Source
AI summary
One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second N-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material. In some cases, the capping material layer may be formed of a material having a Young's modulus of at least 180 GPa.