NTT Memory Access Control for Dilithium Conflict-Free Butterfly Processing
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Solution Overview
Problem
The advent of quantum computers poses a significant threat to the security of existing public-key cryptosystems, necessitating a transition to lattice-based post-quantum cryptography (PQC) to mitigate risks, where current NTT and INTT operations face memory access conflicts and performance bottlenecks.
Innovation Solution
A circuit architecture that controls memory access by reading and writing in specific patterns, using shift registers and a controller to manage coefficients for NTT and INTT operations, reducing the need for shuffling and optimizing memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional NTT and INTT operations are used with sequential memory access, then the implementation is simple, but memory access conflicts and performance bottlenecks occur
Solution Approach 1:
The patent applies preliminary action by pre-planning and controlling memory access patterns before conflicts occur. The controller determines and executes specific read/write patterns (sequential or non-sequential) in advance to prevent memory access conflicts, ensuring that data is available when needed without ad-hoc shuffling operations.
Solution Approach 2:
The patent implements dynamics by making the memory access pattern adaptable and changeable. The controller can dynamically switch between sequential and non-sequential access patterns based on the specific NTT/INTT operation requirements, allowing the system to optimize performance for different computational stages without being locked into a fixed access mode.
2Reliability
If memory shuffling is performed between butterfly operator iterations, then correct data ordering is achieved, but latency increases significantly
Solution Approach 1:
The patent applies continuity of useful action by eliminating idle shuffling operations between computational stages. The memory access controller ensures that data flows continuously from one butterfly operator iteration to the next through carefully coordinated read/write patterns, keeping the computational pipeline full and avoiding interruptions that would increase latency.
Solution Approach 2:
The patent uses the memory access controller as an intermediary that mediates between the computational units and memory storage. This controller acts as a smart buffer that maintains correct data ordering through controlled access patterns rather than physical shuffling, reducing the time data spends in transit while ensuring correctness.
3Productivity
If more memory addresses are accessed in non-sequential patterns, then data availability for next iteration is improved, but memory access conflicts increase
Solution Approach 1:
The patent implements feedback by having the controller monitor and adjust memory access patterns based on the state of computational units and memory contents. The controller receives feedback about which data is needed when and adjusts the read/write patterns accordingly, ensuring optimal data availability while avoiding conflicts through coordinated access timing.
Data Source
AI summary
Generally discussed herein are devices, systems, and methods for performing a number theoretic transform (NTT)/inverse NTT (INTT). A circuit for NTT/INTT can include a memory configured to store polynomial coefficients, butterfly operator circuits coupled to receive the polynomial coefficients and generate, after iterations of operating on the polynomial coefficients, transformed coefficients as outputs, a first subset of the butterfly operator circuits situated in series with each other and in parallel with a second subset of the butterfly operator circuits, shift registers coupled between the butterfly operator circuits and the memory, and a controller coupled to the memory, the controller configured to control which coefficients are provided to the butterfly operator circuits and which addresses of the memory store the outputs.