NTT Processor Memory Banks for RNS Flexibility
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Solution Overview
Problem
Existing NTT processors require large local memory resources to store rotation factors for various finite fields in RNS representation, limiting flexibility and efficiency in cryptographic applications.
Innovation Solution
A stream-based NTT processor architecture that allows simultaneous access to rotation factors across multiple stages, enabling flexible operation across different RNS bases without significant memory overhead, by using a control module to manage memory banks and rotation factor storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If large local memory resources are allocated to store rotation factors for various finite fields, then the NTT processor can support multiple RNS bases, but the memory requirements and device complexity increase significantly
Solution Approach 1:
The memory system is divided into multiple separate memory banks, where each bank is dedicated to storing rotation factors for a specific finite field characteristic. This segmentation allows the processor to access only the required memory bank for the current operation, reducing the effective memory footprint while maintaining support for multiple RNS bases.
Solution Approach 2:
Each memory bank is designed to be universally applicable within its designated finite field, storing rotation factors that can be used across different stages of the NTT processor. This multi-functionality allows the same memory bank to serve multiple processing stages without requiring duplicate storage.
2Ease of operation
If rotation factors are pre-stored in local memory for all possible finite fields, then flexibility in cryptographic operations is improved, but the device complexity and memory overhead increase
Solution Approach 1:
The memory architecture is segmented into multiple banks, each handling a specific finite field characteristic. This segmentation simplifies the control logic for accessing rotation factors, as the controller only needs to select the appropriate bank based on the field characteristic, rather than managing a single large complex memory structure.
Solution Approach 2:
Rotation factors are pre-calculated and stored in the memory banks during system initialization or configuration. This preliminary action eliminates the need for real-time calculation of rotation factors during cryptographic operations, improving operational flexibility while keeping the memory structure manageable.
3Productivity
If a stream-based architecture with simultaneous access to rotation factors is implemented, then processing efficiency is improved, but the memory management complexity increases
Solution Approach 1:
By segmenting the memory into multiple banks, the system enables simultaneous access to rotation factors from different banks during stream processing. Each processing stage can access its required rotation factors from its designated bank without waiting for other stages, improving processing efficiency while keeping individual bank management simple.
Solution Approach 2:
A control module acts as an intermediary between the processing stages and the memory banks. This mediator manages the simultaneous access requests by directing each stage to the appropriate bank, simplifying the memory management complexity while enabling efficient parallel access patterns.
Data Source
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AI summary
The present invention relates to a stream-based NTT processor comprising: a plurality (K) of processing stages (2100, ..., 210K-1) organised in a pipeline (210); a plurality (G+1) of memory banks (220 g , g = 0, G); a read management module (260) for reading, within one memory (MEM g/k ) of a memory bank (220 g ) of the processor, sets of twiddle factors intended for parameterising a processing stage ( 210k ); a write management module (270) for receiving, in the form of successive blocks, a set of twiddle factors and writing said sets of twiddle factors into the memories of a memory bank, the writing being carried out cyclically in the memory banks, each new set of twiddle factors being written into a new memory bank; and a control module for controlling the writing and reading of twiddle factors as well as the progression of data blocks through the processing stages.