NTT Architecture Single Memory Block Lattice Cryptography
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Solution Overview
Problem
Implementing lattice-based cryptographic systems, such as CRYSTALS-Kyber and CRYSTALS-Dilithium, faces challenges in computational efficiency, energy consumption, and data overhead due to the complexity of polynomial multiplication operations, particularly in NTT and INTT computations, which are resource-intensive and require multiple memory blocks.
Innovation Solution
The proposed NTT/INTT architectures utilize a single memory block with radix-4 butterfly units, commutator stages having varying delay depths, and address permutation generators to optimize data permutation, reducing memory accesses and area usage, and eliminate bit-reversed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple memory blocks are used for NTT computations, then data access efficiency is improved, but device area and complexity increase
Solution Approach 1:
The patent segments the NTT computation process into distinct stages (data input stage, computation stage, data output stage) that can be temporally separated. This allows a single memory block to be reused across different stages rather than requiring simultaneous access to multiple memory blocks, thereby reducing area while maintaining computational efficiency
Solution Approach 2:
The patent employs dynamic reconfiguration of the memory block's function across different computation stages. The same memory block dynamically switches between storing input data, intermediate results, and output data depending on the current stage of the NTT computation, eliminating the need for static allocation of multiple memory blocks
2Productivity
If multiple memory blocks are used for NTT computations, then computational throughput is improved, but device complexity increases
Solution Approach 1:
The computation process is segmented into stages that can be executed sequentially through a single memory block. The segmentation allows each stage to complete its operations before the next stage begins, maintaining throughput while avoiding the complexity of managing multiple concurrent memory blocks
Solution Approach 2:
The single memory block is designed to perform multiple functions across different computation stages - serving as input buffer, intermediate storage, and output buffer. This multi-functionality reduces device complexity by eliminating redundant memory structures while preserving computational throughput through efficient resource utilization
3Ease of manufacture
If conventional NTT architectures are used, then implementation is straightforward, but energy consumption is high
Solution Approach 1:
The patent merges the input buffer, intermediate result storage, and output buffer functions into a single memory block. This consolidation reduces the total number of memory access operations and associated control logic, thereby reducing energy consumption while maintaining implementation feasibility through a unified memory interface
Data Source
AI summary
Examples are disclosed that relate to number-theoretic-transform (NTT) architectures and inverse NTT (INTT) architectures for module lattice-based cryptographic algorithms. One example provides a device for performing an NTT for lattice-based cryptographic algorithms. The device comprises a memory block, a read address permutation generator configured to read input values from the memory block, a commutator stage comprising a first commutator layer of commutators and a second commutator layer, a butterfly stage connected to output of the commutator stage, and a write address permutation generator configured to write output values to the memory block.