NUMA-Aware Heap Memory Manager for Multi-Threaded Locality Optimization

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Solution Overview

Problem

In multi-processor systems, especially those with Non-Uniform Memory Access (NUMA) architecture, memory management is inefficient due to bottlenecks caused by shared resource access and limited control over memory allocation, leading to performance degradation and high memory fragmentation.

Innovation Solution

A NUMA-aware heap memory manager that tracks memory block locations to maximize locality by selecting the most local allocation node for memory requests, using multiple cache levels to manage free blocks, and leveraging operating system support to optimize memory allocation and deallocation, thereby reducing remote memory accesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a shared bus-based symmetric multiprocessing (SMP) system is used where multiple processors access memory via a shared bus, then memory access time for any processor is uniform, but the shared memory bus becomes a major performance bottleneck

Engineering Contradiction:
Improveuniform memory access timeVSAvoidsystem performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent segments the unified memory space into node-specific memory regions, where each NUMA node has its own local memory that can be accessed faster by local processors. This segmentation eliminates the shared bus bottleneck by providing dedicated memory paths while maintaining virtual memory abstraction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local quality by allocating memory on the same NUMA node as the executing thread whenever possible, creating local memory regions with faster access characteristics. The system prioritizes local memory allocation to improve performance while maintaining the appearance of uniform access through virtual memory management.

Inventive Principle:
Principle #3Local quality

2Speed

If large caches are used to mitigate the memory bottleneck, then the processor may find data in local cache and avoid memory access, but large data cache may not be a general solution for memory intensive applications that use large areas of memory

Engineering Contradiction:
Improvememory access speedVSAvoidapplicability to memory intensive applications
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent adds a new dimension to memory management by introducing NUMA nodes with hierarchical memory structures. Instead of relying solely on cache (L1/L2/L3), the system creates a memory hierarchy that extends to node-local memory and remote memory, providing multiple levels of storage with different access characteristics to handle various application workloads.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Speed

If NUMA architecture is used with local memory connected directly to each processor, then memory access speed improves, but controlling where memory is allocated becomes challenging and adds burden to programmers

Engineering Contradiction:
Improvememory access speedVSAvoidmemory allocation control
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The patent implements self-service by enabling the memory management library to automatically detect thread affinity and allocate memory on the appropriate NUMA node without programmer intervention. The system monitors thread execution locations and autonomously makes allocation decisions, freeing programmers from the burden of manual NUMA memory management while achieving optimal performance.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent uses feedback mechanisms where the memory management library continuously monitors thread affinity information and allocation patterns. Based on this feedback, the system dynamically adjusts memory allocation decisions to place memory on the most appropriate NUMA node, optimizing performance while maintaining simplicity for applications.

Inventive Principle:
Principle #23Feedback

4Ease of operation

If OS APIs are used for memory allocation, then memory management is provided, but making an OS API call is expensive due to context switch between user mode and system kernel, and APIs have limitations such as large minimum allocation size

Engineering Contradiction:
Improvememory management functionalityVSAvoidAPI call overhead
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-allocating large memory blocks from the OS in advance and maintaining pools of pre-allocated memory within the application. This eliminates the need for frequent OS API calls during normal operation, as the memory management library can satisfy most allocation requests from its pre-allocated pools without context switches.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges the functionality of OS memory management APIs with application-level heap management. The memory management library combines OS allocation capabilities with local pooling strategies, creating a hybrid system that leverages the strengths of both approaches while minimizing the weaknesses of each.

Inventive Principle:
Principle #5Merging (Combining)

5Loss of time

If traditional heap memory manager is used that uses OS API to allocate large memory blocks and divides them into smaller parts, then API call overhead is reduced, but control over memory allocation location is lost leading to remote memory accesses

Engineering Contradiction:
ImproveAPI call overheadVSAvoidmemory access speed
Core Design Contradiction:
Loss of timeVSSpeed

Solution Approach 1:

The patent uses feedback mechanisms where the memory management library continuously monitors thread affinity information and allocation patterns. Based on this feedback, the system dynamically adjusts memory allocation decisions to place memory on the most appropriate NUMA node, optimizing performance while maintaining simplicity for applications.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8245008B2System and method for NUMA-aware heap memory management
Publication Date: 2012.08.14 ADVANCED MICRO DEVICES INC
  • US8245008B2 patent drawing
  • US8245008B2 patent drawing
  • US8245008B2 patent drawing

AI summary

A system and method for allocating memory to multi-threaded programs on a Non-Uniform Memory Access (NUMA) computer system using a NUMA-aware memory heap manager is disclosed. In embodiments, a NUMA-aware memory heap manager may attempt to maximize the locality of memory allocations in a NUMA system by allocating memory blocks that are near, or on the same node, as the thread that requested the memory allocation. A heap manager may keep track of each memory block's location and satisfy allocation requests by determining an allocation node dependent, at least in part, on its locality to that of the requesting thread. When possible, a heap manger may attempt to allocate memory on the same node as the requesting thread. The heap manager may be non-application-specific, may employ multiple levels of free block caching, and/or may employ various listings that associate given memory blocks with each NUMA node.