NUMA Computer IO Performance Optimization via Pattern Management

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Solution Overview

Problem

In computer systems with Non-Uniform Memory Access (NUMA) architecture, IO performance is often hindered by high CPU capacity utilization, leading to drops in performance due to increased CPU load, access delays between IO devices and memory, and CPU-memory access inefficiencies, which existing methods fail to fully optimize.

Innovation Solution

A system that determines the optimal placement of CPUs and memories by using pattern management information to analyze and apply policies for IO performance, including policies on memory allocation, driver management, and computation core allocation, to maximize IO performance across multiple patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If CPU capacity utilization is increased to handle frequent IO activation processing and IO response processing, then IO performance deteriorates due to high CPU load

Engineering Contradiction:
ImproveIO performanceVSAvoidCPU load
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the CPU workload by separating IO activation processing from IO response processing. IO activation processing is handled by a dedicated CPU, while IO response processing is handled by another CPU. This segmentation reduces the CPU load on individual processors and prevents performance deterioration caused by high capacity utilization.

Inventive Principle:
Principle #1Segmentation

2Reliability

If CPUs are placed in a dispersed manner to avoid high CPU load, then access time between CPU and memory increases

Engineering Contradiction:
ImproveCPU loadVSAvoidaccess time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by creating different placement strategies for different CPU types. Local CPUs are placed close to local memory for fast access, while remote CPUs are placed close to remote memory. This allows each CPU to have optimal local access to memory, reducing access time while maintaining dispersed placement for load balancing.

Inventive Principle:
Principle #3Local quality

3Productivity

If block size of IO access is increased, then number of DMA transfers increases which lowers IO performance

Engineering Contradiction:
ImproveIO performanceVSAvoidnumber of DMA transfers
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent dynamically adjusts the block size of IO access based on system conditions. The block size is not fixed but can be changed according to CPU load, memory availability, and IO patterns. This dynamic adjustment optimizes the balance between reducing the number of DMA transfers and maintaining efficient IO performance.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10209888B2Computer and optimization method
Publication Date: 2019.02.19 HITACHI VANTARA LTD
  • US10209888B2 patent drawing
  • US10209888B2 patent drawing
  • US10209888B2 patent drawing

AI summary

A computer has processors each including computation cores; memories, and an IO device, and includes NUMA nodes. The computer holds pattern management information to manage patterns and comprises a control module to determine a pattern to be applied to the computer. The pattern management information includes policy information including a policy on placement of a transfer-use memory area in the NUMA nodes, a policy on the placement of driver management information in the NUMA nodes, and a policy on allocation of computation cores that execute data transfer in the NUMA nodes, for each of the plurality of patterns. The control module applies each of the patterns to the computer based on the pattern management information, to measure IO performance in each of the patterns, and determine a pattern being highest in IO performance as a pattern to be applied to the computer.