NUMA Memory Distribution via Weighted Locality Tracking

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Solution Overview

Problem

Determining an optimal memory distribution across multiple non-uniform memory access (NUMA) nodes is challenging due to varying memory access latencies and the difficulty in accurately sampling memory accesses, which can lead to suboptimal processing performance.

Innovation Solution

The system determines weighted locality values by measuring memory access fractions and processing times across multiple processing nodes, using these values to redistribute memory and minimize access to shared memory, thereby optimizing processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory is distributed across multiple NUMA nodes to handle distributed processes, then system capacity and adaptability are improved, but memory access latency increases due to shared memory access

Engineering Contradiction:
Improvedistributed process handlingVSAvoidmemory access latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements local memory allocation within each NUMA node, where memory is locally attached to processing units. This creates different quality levels of memory access: local memory provides fast access while shared memory across nodes provides distributed capacity. The system optimizes by preferentially allocating memory locally to each processing unit, thereby maintaining fast access speeds while enabling distributed process handling across multiple nodes.

Inventive Principle:
Principle #3Local quality

2Device complexity

If simple memory distribution is used across NUMA nodes, then device complexity is reduced, but processing performance deteriorates due to suboptimal memory allocation

Engineering Contradiction:
Improvememory distribution mechanismVSAvoidprocessing performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements a feedback mechanism that monitors memory access patterns and dynamically adjusts memory distribution across NUMA nodes. The system tracks which processing units access which memory regions and uses this information to optimize memory allocation, ensuring that frequently accessed memory is placed in locations that minimize access latency while maintaining balanced distribution across nodes.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The memory distribution system is designed to be dynamic rather than static. It continuously adapts memory allocation based on changing workloads and access patterns, allowing the system to optimize performance for different process distributions and memory access behaviors while maintaining manageable complexity through automated adjustment.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If processes are distributed across multiple NUMA nodes, then system capacity is improved, but determining optimal memory distribution becomes more difficult

Engineering Contradiction:
Improvesystem capacityVSAvoidmemory distribution determination
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent implements self-service mechanisms where the memory distribution system automatically monitors its own performance and makes adjustments without external intervention. The system tracks memory access patterns, identifies optimization opportunities, and redistributes memory across NUMA nodes autonomously, thereby managing the complexity of optimal distribution determination while supporting increased system capacity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10198370B2Memory distribution across multiple non-uniform memory access nodes
Publication Date: 2019.02.05 RED HAT INC
  • US10198370B2 patent drawing
  • US10198370B2 patent drawing
  • US10198370B2 patent drawing

AI summary

A system, methods, and apparatus for determining memory distribution across multiple non-uniform memory access processing nodes are disclosed. An apparatus includes processing nodes, each including processing units and main memory serving as local memory. A bus connects the processing units of each processing node to different main memory of a different processing node as shared memory. Access to local memory has lower memory access latency than access to shared memory. The processing nodes execute threads distributed across the processing nodes, and detect memory accesses made from each processing node for each thread. The processing nodes determine locality values for the thread that represent the fraction of memory accesses made from the processing nodes, and determine processing time values for the threads for a sampling period. The processing nodes determine weighted locality values for the threads, and determine a memory distribution across the processing nodes based on the weighted locality values.