NUMA Memory Page Replication for Low-Latency Access
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Solution Overview
Problem
Non-unified memory architectures (NUMA) in portable computing devices result in higher latency due to the need for processors to access data in near or far DRAM, leading to performance issues.
Innovation Solution
The system allocates memory by identifying and mapping free physical page pairs across multiple SoCs to a single virtual page address, using a modified page table entry with a copy attribute field to replicate memory data, enabling low-latency access across multiple processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If processors access data in far DRAM through inter-chip interface in NUMA architecture, then memory capacity is increased, but access latency increases
Solution Approach 1:
The patent implements memory page replication by creating copies of physical memory pages across multiple DRAM devices on different chips. When a page is accessed, the system determines if a copy exists in the requesting processor's local DRAM, and if so, accesses the local copy instead of the remote original, thereby reducing access latency while maintaining increased memory capacity through the NUMA architecture
Solution Approach 2:
The system proactively replicates memory pages to local DRAM before they are needed by the local processor. The memory management unit monitors access patterns and pre-loads pages into local memory, so when the processor needs the data, it is already available locally, eliminating the latency penalty of far DRAM access
2Loss of time
If memory pages are replicated across multiple DRAM devices, then access latency is reduced, but memory management complexity increases
Solution Approach 1:
The patent introduces a memory management unit (MMU) as an intermediary between the processor and the memory system. The MMU automatically handles page replication, tracking which pages exist in which DRAM devices, and intercepting memory access requests to determine whether to access local copies or remote originals. This intermediary manages the complexity of replicated memory management, shielding the processor from the complexity while enabling low-latency access
Data Source
AI summary
Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture. One embodiment of a method comprises: receiving from a process executing on a first system on chip (SoC) a request for a virtual memory page, the first SoC electrically coupled to a second SoC via an interchip interface, the first SoC electrically coupled to a first local volatile memory device via a first high-performance bus and the second SoC electrically coupled to a second local volatile memory device via a second high-performance bus; determining a free physical page pair comprising a same physical address available on the first and second local volatile memory devices; and mapping the free physical page pair to a single virtual page address.