NUMA Memory Replication for Read-Only Code

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Solution Overview

Problem

Modern CPUs face performance issues due to the faster operation compared to main memory, leading to throughput and latency problems, especially in NUMA systems where memory access time depends on the physical location of memory relative to the processor, and increased memory bandwidth consumption with larger executable codes.

Innovation Solution

A kernel mechanism is introduced to replicate memory used for executable, read-only code across two or more CPU sockets, eliminating the need for NUMA link traffic during code loading, thereby improving performance and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If separate memory is provided for each processor in NUMA systems, then memory access speed for local memory is improved, but memory bandwidth consumption increases when loading large executable codes

Engineering Contradiction:

Improvememory access speedVSAvoidmemory bandwidth consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies the copying principle by creating duplicate copies of executable code in the local memory of each processor socket. Instead of having processors fetch code from remote memory over NUMA links, each socket has a local copy of the code in its attached memory, eliminating the need for bandwidth-intensive remote access while maintaining fast local access speeds

Inventive Principle:

Principle #26Copying

2Quantity of substance

If executable code is loaded from remote memory in NUMA systems, then memory capacity is increased, but throughput performance deteriorates due to NUMA link traffic

Engineering Contradiction:

Improvememory capacityVSAvoidthroughput performance

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent applies local quality by making the memory access characteristics location-dependent - executable code is stored in local memory at each processor socket, ensuring that code execution always occurs from locally-available memory rather than remote memory. This creates a quality difference where local code execution paths are optimized for high throughput while remote memory remains available for other purposes

Inventive Principle:

Principle #3Local quality

3Speed

If more memory is allocated to each processor socket, then local memory access performance is improved, but system complexity increases

Engineering Contradiction:

Improvelocal memory access performanceVSAvoidsystem complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent applies partial action by selectively replicating only executable code in local memory rather than replicating all memory contents. This partial replication approach provides the performance benefits of local memory access for code execution while avoiding the excessive memory requirements and system complexity that would result from fully replicating all memory across all processors

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS10776046B1Optimized non-uniform memory access

Publication Date: 2020.09.15 PURE STORAGE INC

AI summary

In one implementation, a method includes receiving code associated with two or more cores of a storage array controller. The method further includes determining, by the storage array controller, that the code is executable and read-only. The method further includes loading, based on the determination, the code into two or more memory pages corresponding to the two or more cores, wherein each of the two or more memory pages is local to each of the two or more cores, respectively.