NUMA Memory Access with Ethernet Switch Fabric Coherence
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Solution Overview
Problem
Conventional data processing systems are inefficient in handling petabyte-scale data sets, leading to impractical or impossible analysis due to inadequate high-bandwidth access and parallel processing capabilities.
Innovation Solution
A scalable data processing system architecture featuring multiple CPU subsystems, memory complexes, and an Ethernet switch fabric, with software-implemented flash translation layer policies and replication interfaces, enabling efficient parallel access and data replication across interconnected memory leaves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional data processing systems are used, then system simplicity is maintained, but high-bandwidth access to petabyte-scale data sets is inefficient or impossible
Solution Approach 1:
The system is divided into multiple processing nodes, each with its own memory controllers and cache memory units. This segmentation allows parallel access to data across multiple nodes, achieving high-bandwidth access to petabyte-scale data sets while maintaining manageable complexity at each node level.
Solution Approach 2:
The patent introduces a multi-dimensional memory hierarchy with cache memory units at each processing node and distributed memory across the network. This dimensional expansion from single-node to multi-node architecture enables scalable high-bandwidth access without linearly increasing overall system complexity.
2Productivity
If multiple processing nodes are introduced to enable parallel processing, then processing throughput is improved, but maintaining cache coherence becomes more difficult
Solution Approach 1:
The system implements a feedback mechanism where cache memory units monitor and track data state across processing nodes. When data is modified in one node's cache, the system automatically manages coherence by invalidating or updating corresponding caches in other nodes, enabling parallel processing while maintaining data consistency.
Solution Approach 2:
The patent introduces intermediary structures including memory controllers and coherence management logic that mediate between processing nodes and distributed memory. These intermediaries handle the complex cache coherence protocols, allowing processing nodes to operate in parallel while the intermediaries maintain system-wide data consistency.
3Adaptability or versatility
If distributed memory architecture is implemented across multiple nodes, then data access scalability is improved, but access time non-uniformity increases
Solution Approach 1:
The system implements local cache memory units at each processing node that store frequently accessed data locally. This local quality optimization reduces access time for local data while maintaining scalability, as nodes preferentially access their own caches before reaching out to remote memory, thereby reducing the impact of non-uniform access times.
Solution Approach 2:
The patent employs preliminary data placement and caching strategies where data is pre-loaded into local cache memory units before being needed by processing nodes. This preliminary action reduces the variability in access times by ensuring that frequently accessed data is already positioned in optimal locations, minimizing remote access requirements.
Data Source
AI summary
According to one embodiment, a data processing system includes a plurality of processors, each of the processors being coupled to each of remaining processors via a processor interconnect, a plurality of memory controllers, each memory controller corresponding to one of the processors, a plurality of memory targets, each memory target includes one or more branches and a plurality of memory leaves for storing data, and an Ethernet switch fabric coupled to the memory controllers and the memory targets. When a first of the memory controllers writes data to a first of the memory leaves, the first memory controller sends a cache coherence message to remaining ones of the memory controllers to indicate that the data stored in the first memory leaf has been updated, such that any of the remaining memory controllers can update its cache by fetching the data from the first memory leaf.