NUMA-Aware Network Queue Allocation for Latency Reduction

The patent applies local quality by allocating queue pairs to node local memory instead of distributing them across cores in a NUMA system. This ensures that memory accesses are localized to the same node, reducing remote memory accesses and associated latency. Each node maintains its own queue pairs in local memory, creating a localized processing architecture that minimizes cross-node memory traffic.

The patent merges queue pair allocations at the node level rather than maintaining separate queue pairs for each core. By consolidating queue pairs in node local memory and having multiple cores share access to these node-level queue pairs, the system reduces total memory allocation while maintaining processing capability. This merging approach eliminates redundant queue pair instances that would exist if each core had its own dedicated queue pairs.

The patent eliminates cacheline thrashing by ensuring that queue pairs and their associated data structures reside in node local memory. This localizes packet processing operations to individual nodes, preventing cacheline conflicts between nodes. By making the memory allocation local rather than distributed, the system maintains high packet processing throughput without the harmful effect of inter-node cacheline thrashing.