NUMA Aware Network Interface Direct NIC-to-NIC Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NUMA platform architectures experience increased processor overhead and interconnect traffic due to the involvement of multiple hardware components and software entities when handling packets destined for memory resources on different nodes, leading to additional packet transfer latency and cache pollution.
Innovation Solution
Implementing NUMA aware network interfaces that enable direct NIC-to-NIC interconnects to transfer packets received at one node destined for memory resources on another node, thereby eliminating the need for intermediate copying and processing, and reducing bandwidth consumption and software entity involvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packets are handled through multiple hardware components and software entities in conventional NUMA architectures, then packet routing and memory access control is achieved, but processor overhead and interconnect traffic increase
Solution Approach 1:
The patent extracts the packet routing decision logic from the CPU and software entities and embeds it directly into the NIC hardware. The NIC now contains embedded logic that can autonomously determine the destination node and initiate direct transfers without requiring intermediate copying through multiple hardware components or software processing steps, thereby reducing overall system complexity while maintaining routing accuracy
Solution Approach 2:
The NIC is designed with self-service capabilities including embedded routing logic and direct transfer initiation functions. The NIC can autonomously perform packet classification, destination determination, and direct memory access without requiring extensive software entity involvement or multiple hardware component intermediaries, reducing processor overhead and interconnect traffic
2Reliability
If packets are copied through intermediate nodes and processed by multiple entities, then packet handling completeness is ensured, but packet transfer latency increases
Solution Approach 1:
The patent implements preliminary action by having the NIC perform packet classification and destination node determination before the packet enters the traditional processing pipeline. The embedded routing logic in the NIC pre-determines the optimal transfer path and initiates direct transfers to the destination node's memory, eliminating subsequent intermediate copying steps and reducing overall packet transfer latency while ensuring handling completeness
Solution Approach 2:
The patent enables packets to skip intermediate copying steps by implementing direct NIC-to-NIC transfer mechanisms. Instead of routing packets through multiple hardware components and software entities for copying, the system allows packets to rush through the system via direct memory access and transfer, reducing the time spent in intermediate processing stages while maintaining complete packet handling
3Adaptability or versatility
If packets are copied to intermediate memory resources, then data transfer flexibility is achieved, but interconnect bandwidth consumption increases
Solution Approach 1:
The patent extracts the data transfer function from the traditional CPU-mediated memory copy process and implements it directly at the NIC level. The NIC contains embedded logic that can directly transfer packet data to the destination node's memory resources without requiring intermediate copying through the CPU or other hardware components, thereby reducing interconnect bandwidth consumption while maintaining transfer flexibility
Solution Approach 2:
The patent introduces a direct NIC-to-NIC transfer mechanism that acts as an efficient intermediary between source and destination nodes. This direct transfer pathway eliminates the need for packets to traverse through intermediate memory resources and multiple hardware components, reducing the total interconnect bandwidth required while preserving the flexibility to route packets to any destination node
Data Source
AI summary
Methods, apparatus, and computer platforms and architectures employing node aware network interfaces are disclosed. The methods and apparatus may be implemented on computer platforms such as those employing a Non-uniform Memory Access (NUMA) architecture including a plurality of nodes, each node comprising a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a NUMA aware Network Interface Controller (NIC). Under one method, a packet is received from a network at a first NIC comprising a component of a first node, and a determination is made that packet data for the packet is to be forwarded to a second node including a second NIC. The packet data is then forwarded from the first NIC to the second NIC via a NIC-to-NIC interconnect link. Upon being received at the second NIC, processing of the packet (data) is handled as if the packet was received from the network at the second NIC.