NUMA Scheduling via Inter-VCPU Memory Access Estimation
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Solution Overview
Problem
In non-uniform memory access (NUMA) systems, achieving memory locality is challenging due to high interconnect latency and remote memory access penalties, which can lead to performance degradation, especially in multi-core architectures where many cores can stall waiting for memory access, undermining the benefits of concurrent execution.
Innovation Solution
A novel method involving statistical sampling of memory accesses to estimate inter-vCPU sharing and page fault frequencies, allowing for proactive migration of virtual machines (VMs) and dynamic scheduling to maximize memory locality, thereby reducing remote access and improving performance by ensuring that memory accesses occur locally within the same NUMA node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple processor cores share a single memory bus in traditional SMP systems, then memory access is coordinated centrally, but performance degrades due to increased contention and bottleneck effects
Solution Approach 1:
The system segments the memory architecture into multiple independent memory controllers, each associated with specific CPU cores. This divides the single memory bus into multiple parallel memory channels, reducing contention and allowing simultaneous memory accesses across different cores without blocking each other.
Solution Approach 2:
Each CPU core or core group is assigned a dedicated local memory controller and memory channel, creating localized memory access paths. This ensures that each core has direct access to memory without sharing the bottleneck of a centralized bus, improving overall processing speed while maintaining coordinated memory access through localized control.
2Productivity
If statistical sampling of memory accesses is performed to estimate inter-vCPU sharing, then memory locality optimization is achieved, but system overhead increases due to sampling and analysis operations
Solution Approach 1:
Instead of tracking every memory access completely, the system performs partial sampling of memory accesses to estimate inter-vCPU sharing patterns. This partial action approach provides sufficient information for optimization decisions while significantly reducing the overhead compared to full tracking, achieving a balance between optimization benefit and cost.
Solution Approach 2:
The system uses statistical sampling to continuously monitor memory access patterns and feeds this information back to the scheduler. Based on this feedback, the scheduler dynamically adjusts vCPU placement and memory allocation strategies to optimize memory locality, creating a closed-loop system that adapts to changing workload patterns.
Data Source
AI summary
In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.