NUMA Processor Synchronization via Dedicated Signal Line
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Solution Overview
Problem
In systems with non-uniform memory access (NUMA), the processing performance deteriorates when processes executed by processors in different nodes synchronize, particularly due to increased waiting times during memory synchronization processes, especially when the chunk size is small.
Innovation Solution
A parallel operation system that employs a signal line for synchronization between processors in different nodes, executing a CPU synchronization process instead of the traditional memory synchronization process to improve performance, and dynamically decides between CPU and memory synchronization methods based on chunk size and iteration counts using synchronization-method-specific performance information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory synchronization process is used for synchronizing processes between processors in different NUMA nodes, then synchronization is achieved, but processing performance deteriorates due to increased waiting times
Solution Approach 1:
The patent introduces a signal line as an intermediary communication channel between processors in different NUMA nodes. Instead of using memory as the synchronization medium, the signal line directly transmits synchronization signals between processors, eliminating the performance penalty of cross-node memory access while maintaining reliable synchronization.
Solution Approach 2:
The patent replaces the memory-based synchronization mechanism with a direct signal line connection. This substitution changes the synchronization mechanism from one that relies on memory access (which suffers from NUMA performance issues) to one that uses dedicated communication pathways, thereby improving processing performance while maintaining synchronization reliability.
2Measurement precision
If memory synchronization process is used with small chunk size, then fine-grained synchronization is achieved, but waiting time increases significantly
Solution Approach 1:
The signal line acts as a dedicated intermediary for transmitting synchronization signals, allowing fine-grained synchronization to occur without the overhead of memory access. Each synchronization event can be signaled immediately through the signal line rather than waiting for memory operations to complete, thus reducing waiting time while maintaining fine-grained control.
Solution Approach 2:
The signal line is pre-established between processors, allowing synchronization signals to be transmitted immediately when needed. This eliminates the need for preliminary memory allocation and setup that would otherwise be required for fine-grained synchronization, reducing the waiting time associated with small chunk sizes.
3Productivity
If CPU synchronization process is used instead of memory synchronization process, then processing performance is improved, but system complexity increases
Solution Approach 1:
The signal line serves multiple functions: it provides synchronization signals between processors, enables communication for coordination, and can potentially carry other control signals. This multi-functionality reduces the need for separate dedicated mechanisms for each function, thereby limiting the increase in system complexity while achieving CPU-based synchronization.
Solution Approach 2:
The patent merges the synchronization function with the existing processor communication infrastructure. Rather than adding completely separate synchronization hardware, the signal line is integrated into the processor interconnect, combining communication and synchronization functions to minimize the increase in system complexity.
Data Source
AI summary
A parallel operation system includes a first node including a first processor configured to execute a first process, a second processor configured to execute a second process, and a first memory, and a second node including a third processor configured to execute a third process, a fourth processor configured to execute a fourth process, and a second memory, and a first signal line that transfers synchronization information between at least one of the first and second processors and at least one of the third and fourth processors, wherein when the first process is to be synchronized with the third process, at least one of the first and the third processors using the first signal line to execute a first synchronization process.