NUMA-Aware Statistics Counters for Scalable Multicore Systems

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Solution Overview

Problem

In multicore architectures with Non-Uniform Memory Access (NUMA) systems, shared statistics counters face scalability bottlenecks and inaccuracies due to contention between threads, leading to increased latency and loss of updates, especially in systems with distributed cache-coherent NUMA (CC-NUMA) properties.

Innovation Solution

Implementing scalable statistics counters by splitting counters into multiple components, using probabilistic counters, and employing adaptive techniques such as node affinity and randomized backoff to reduce contention, allowing consecutive updates on a single node and minimizing cache misses, while maintaining accuracy and low space overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If shared statistics counters are used in NUMA systems, then performance monitoring and diagnostics are enabled, but scalability bottlenecks and latency increase due to invalidation traffic on every modification

Engineering Contradiction:
Improveaccuracy of statistics countersVSAvoidscalability of counter updates
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the shared counter into multiple per-thread counters, each maintained locally by a thread. This segmentation eliminates the need for invalidation traffic when threads update their local counters, while still enabling accurate aggregate statistics collection by summing individual thread counters when needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each thread maintains its own local counter with full update privileges, eliminating remote access latency and invalidation traffic. The local counter provides the same functional capability as a shared counter but with superior performance characteristics for the local thread.

Inventive Principle:
Principle #3Local quality

2Reliability

If naive concurrent counter implementations are used, then thread-safe counting is achieved, but performance degrades due to contention and invalidation traffic as thread counts grow

Engineering Contradiction:
Improvethread-safety of counter updatesVSAvoidperformance under high thread contention
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The counter is segmented into independent per-thread counters, eliminating contention between threads. Each thread safely updates only its own counter without requiring synchronization or invalidation protocols, achieving both thread-safety and high performance under contention.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each thread independently maintains and updates its own counter without requiring services from other threads or centralized coordination. This self-service approach eliminates the need for invalidation traffic and synchronization overhead while maintaining thread-safety.

Inventive Principle:
Principle #25Self-service

3Productivity

If updates are moved outside transactions to reduce contention, then transactional success rates improve, but the semantics of the program are changed

Engineering Contradiction:
Improvetransactional success rateVSAvoidprogram semantics
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

By segmenting the counter into per-thread counters, the patent allows updates to remain within transactions without causing contention. Each thread's update to its own counter is independent and does not conflict with other threads, maintaining both transactional success rates and original program semantics.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP2936313B1System and method for implementing NUMA-aware statistics counters
Publication Date: 2019.09.25 ORACLE INT CORP
  • EP2936313B1 patent drawingFigure 1
  • EP2936313B1 patent drawingFigure 2
  • EP2936313B1 patent drawingFigure 3A~3C

AI summary

The systems and methods described herein may be used to implement scalable statistics counters suitable for use in systems that employ a NUMA style memory architecture. The counters may be implemented as data structures that include a count value portion and a node identifier portion. The counters may be accessible within transactions. The node identifier portion may identify a node on which a thread that most recently incremented the counter was executing or one on which a thread that has requested priority to increment the shared counter was executing. Threads executing on identified nodes may have higher priority to increment the counter than other threads. Threads executing on other nodes may delay their attempts to increment the counter, thus encouraging consecutive updates from threads on a single node. Impatient threads may attempt to update the node identifier portion or may update an anti-starvation variable to indicate a request for priority.