Number Theoretic Transform Circuit for Parallel Polynomial Operations
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Solution Overview
Problem
Conventional number theoretic transform architectures in quantum cryptography suffer from high hardware resource consumption, lower parallelism, longer clock cycles, and increased complexity due to the use of multiple operation units with multipliers and numerous modular operations, posing challenges for efficient polynomial operations in lattice-based cryptography.
Innovation Solution
A number theoretic transform operation circuit comprising a first and second transform unit and k operation units, each with a multiplier, Boolean operations, multiplexers, an adder, and a subtractor, allowing parallel processing of coefficients to reduce clock cycles and hardware resource consumption, while supporting polynomial operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional number theoretic transform architecture uses multiple operation units with multipliers to support Montgomery modular multiplication, then the operation capability is improved, but the hardware resource consumption increases and device complexity increases
Solution Approach 1:
The patent changes the operational parameters by eliminating comparison operations through analysis of input and output range values. This reduces the number of elements in operation units and simplifies the hardware architecture while maintaining polynomial operation capabilities in lattice cryptography
Solution Approach 2:
The patent extracts and eliminates unnecessary comparison operations from the number theoretic transform architecture. By analyzing the range values of inputs and outputs, the design removes redundant comparison elements, thereby reducing hardware resource consumption and device complexity
2Area of stationary object
If customized number theoretic transform architecture uses very few operation units to reduce area, then the area of hardware is reduced, but the degree of parallelization decreases and clock cycle increases
Solution Approach 1:
The patent segments the number theoretic transform operation into k operation units that can process 2k coefficients in parallel. Each operation unit handles specific polynomial operations independently, achieving high degree of parallelization while using a manageable number of operation units
Solution Approach 2:
The patent transforms the sequential processing approach into parallel processing by organizing operation units to handle multiple coefficients simultaneously. This dimensional change from sequential to parallel operation increases productivity without proportionally increasing hardware area
3Measurement precision
If conventional number theoretic transform architecture adopts a large number of modular operations with comparison operations, then the operation precision is maintained, but the complexity of operations increases and clock cycle increases
Solution Approach 1:
The patent extracts and removes unnecessary comparison operations from the modular operation chain. By analyzing the mathematical properties and range values of inputs and outputs in lattice cryptography operations, the design eliminates redundant comparisons while preserving the necessary precision for cryptographic operations
Solution Approach 2:
The patent changes the operational parameters by optimizing the number and type of operations based on input-output range analysis. This reduces the complexity of modular operations while maintaining the precision required for cryptographic applications
Data Source
AI summary
A number theoretic transform operation circuit includes first and second number theoretic transform units and k operation units. The first number theoretic transform unit receives 2k first coefficients in parallel and transforms an order thereof to output 2k second coefficients in parallel. k is a positive integer. The second theoretic transform unit receives 2k third coefficients in parallel and transforms an order thereof to output 2k fourth coefficients in parallel. The k operation units are coupled in parallel between the first and second number theoretic transform units and receive the 2k second coefficients to execute a polynomial operation and output the 2k third coefficients. Each k operation unit sequentially receives two of the 2k second coefficients to execute the polynomial operation and outputs two of the 2k third coefficients. Each operation unit includes a multiplier, two Boolean operation elements, two multiplexers, an adder, and a subtractor.