Numerical Delay Model for Circuit Synthesis Timing
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Solution Overview
Problem
Existing circuit synthesis approaches face inefficiencies and poor quality results due to inaccurate delay modeling, particularly for large circuit designs with many timing constraints across process corners and modes, leading to numerous timing violations.
Innovation Solution
The development of numerical delay models based on discretized delay models, which represent delay behavior using discrete data points in multi-dimensional spaces, allowing for accurate optimization of circuit implementations with minimal timing violations by determining specific and generic logical and parasitic delay values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error based circuit synthesis approaches are used to optimize cell sizes, then timing constraints can be checked across process corners and modes, but the synthesis process takes too long to complete for large circuit designs
Solution Approach 1:
The patent pre-computes delay values for all possible cell size combinations and stores them in lookup tables before the actual synthesis process. This preliminary action allows the synthesis tool to quickly retrieve delay information without performing iterative simulations, dramatically reducing synthesis time while maintaining accurate timing constraint checking across all process corners and modes.
Solution Approach 2:
The patent segments the delay characterization into discrete cell size categories (e.g., minimum, 1.2x, 1.5x, 2x, etc.) and pre-characterizes each segment independently. This segmentation allows parallel processing of different cell sizes and enables efficient storage in structured lookup tables, improving both the speed and organization of delay information retrieval during synthesis.
2Productivity
If the linear delay model (d=g·h+p) is used for circuit synthesis, then the synthesis process is computationally efficient, but the model is inaccurate and produces approximate circuit implementations with many timing violations
Solution Approach 1:
The patent transforms the continuous delay parameters into discrete, pre-computed values for specific cell size categories. By changing the parameter representation from continuous mathematical models to discrete lookup table entries, the patent achieves both computational efficiency (quick table lookups) and high accuracy (precise measured delay values) for timing constraint verification.
Solution Approach 2:
The patent creates simplified copy representations of the actual delay behavior by pre-measuring delays for representative cell sizes and storing these as lookup tables. These copies capture the essential delay characteristics without requiring complex real-time calculations, enabling fast synthesis while maintaining accuracy through the use of empirically derived delay values.
3Reliability
If accurate delay modeling is implemented to reduce timing violations, then circuit implementation quality improves, but the complexity of delay model derivation and maintenance increases
Solution Approach 1:
The patent creates universal lookup tables that can be used across multiple design scenarios and process corners. By deriving delay models that are applicable to various cell types and sizing scenarios using a unified methodology, the patent reduces the need for separate complex models for each case, thereby maintaining accuracy while managing complexity through reuse and standardization.
Solution Approach 2:
The patent implements automated delay model extraction that uses the technology library cell definitions and standard cell characterization data to automatically generate the lookup tables. This self-service approach eliminates manual model derivation and reduces maintenance complexity, as the system automatically updates delay models when library cells are modified, ensuring accuracy without increasing operational complexity.
Data Source
AI summary
Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.