Non-Volatile Buffer Wear Management for SSD Throughput
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Solution Overview
Problem
Non-volatile memory systems, such as NAND flash memory, face limitations in the number of write/erase cycles, leading to reduced operational guarantees and increased data access times as storage density increases, making it challenging to balance throughput and storage capacity without exceeding the maximum allowable write/erase cycles.
Innovation Solution
A memory system with a controller that allocates blocks to a buffer based on wear-out levels, using a hybrid method that combines SLC-dedicated and SLC/TLC-shared block methods to optimize the allocation ratio, allowing for efficient data writing and garbage collection to extend the lifespan of the SSD while maintaining high throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in a memory cell increases to increase storage density, then the memory capacity increases, but the time required to write and read data becomes longer
Solution Approach 1:
The patent segments the non-volatile memory into multiple blocks with different write operation modes (SLC mode for 1 bit per cell, MLC mode for 2 bits per cell, TLC mode for 3 bits per cell). This segmentation allows the system to choose appropriate storage density and access speed based on specific data requirements, resolving the contradiction between capacity and access time.
Solution Approach 2:
The patent dynamically selects write operations based on wear-out levels and data characteristics. The controller can switch between SLC, MLC, and TLC write modes adaptively, allowing the system to optimize between speed and capacity in real-time based on current block conditions and workload requirements.
2Productivity
If throughput is increased by selective write operations, then data writing speed improves, but the total amount of data that can be written before reaching maximum W/E cycles decreases
Solution Approach 1:
The patent changes the wear-out parameter threshold dynamically. When block wear-out levels are low, the system uses SLC writes for high throughput. When wear-out levels increase, the system transitions to MLC or TLC writes. This parameter change allows the system to maximize both throughput and total data capacity over the device lifetime.
Solution Approach 2:
The patent implements feedback through wear-out level monitoring. The controller continuously tracks the number of W/E cycles for each block and uses this feedback to determine the appropriate write operation mode, ensuring optimal balance between throughput and total data capacity throughout the device's operational life.
3Productivity
If SLC write operation is used to increase throughput, then write speed improves, but the allowable number of write/erase cycles is consumed faster
Solution Approach 1:
The patent dynamically adjusts the write operation mode based on real-time wear-out level monitoring. The system starts with SLC writes for maximum speed, then transitions to MLC or TLC writes as wear-out levels increase, thereby extending operational lifespan while maintaining acceptable throughput.
Solution Approach 2:
The patent changes the write operation parameter (from SLC to MLC to TLC) based on wear-out level thresholds. This parameter change allows the system to reduce write speed only when necessary to preserve reliability, optimizing the balance between throughput and operational lifespan.
Data Source
AI summary
According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.