Direct Non-Volatile Cache Access via PCIe Switch
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Solution Overview
Problem
The existing storage systems face limitations in data transmission due to shared data bus constraints, which hinder efficient data movement from traditional storage devices to non-volatile caches, leading to bottlenecks as the number of storage devices increases.
Innovation Solution
Implementing a direct access mode and manager system that allows non-volatile caches to access storage devices directly through a PCIe switch, bypassing the CPU local memory, using a direct data engine and arbitrator to manage data flows and switch configurations, enabling scalable and efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If non-volatile cache shares the same data bus as other block storage devices, then the data bus structure remains simple and compatible, but data transmission speed and efficiency are limited by bus constraints
Solution Approach 1:
The patent segments the data access path by introducing a dedicated PCIe-based data bus for non-volatile cache that is separate from the traditional SATA/NAS storage bus. This segmentation allows high-speed PCIe traffic to bypass the constrained shared data bus, thereby increasing data transmission speed without requiring complete restructuring of the entire storage system architecture.
Solution Approach 2:
The patent introduces a PCIe switch as an intermediary device that enables direct communication between the non-volatile cache and storage devices. This intermediary component manages the data flow between different bus types (PCIe and SATA), allowing high-speed access while maintaining compatibility with existing storage infrastructure without requiring full architectural complexity.
2Productivity
If direct access mode is implemented for non-volatile cache, then data access efficiency improves by bypassing CPU local memory, but system architecture complexity increases
Solution Approach 1:
The patent implements self-service by enabling the non-volatile cache to directly access storage devices through PCIe without requiring CPU intervention or involvement of CPU local memory. The cache system autonomously manages its own data access operations, thereby improving productivity while the modular PCIe implementation keeps architecture complexity manageable.
Solution Approach 2:
The patent introduces dynamic access modes that allow the system to switch between traditional CPU-mediated access and direct PCIe-based access based on operational needs. This dynamic capability improves data access efficiency when direct access is utilized, while maintaining architectural flexibility that prevents excessive complexity by allowing selective activation of direct access paths.
3Adaptability or versatility
If multiple storage devices connect through shared data bus, then system scalability is maintained, but bandwidth limitations arise as number of devices increases
Solution Approach 1:
The patent adds another dimension to the storage architecture by introducing a parallel PCIe-based data path alongside the traditional shared SATA bus. This dimensional addition allows multiple storage devices to connect through high-bandwidth PCIe channels independently, thereby maintaining system scalability while overcoming bandwidth limitations that arise in shared bus configurations.
Data Source
AI summary
A system and method of providing direct data access between a non-volatile cache and a set of storage devices in a computing system. A system is disclosed that includes: a processing core embedded in a controller card that controls a non-volatile cache system; and a direct access manager for directing the processing core, wherein the direct access manager includes: a switch configuration system that includes logic to control a switch for either a direct access mode or a CPU access mode, wherein the switch couples each of the storage devices, a local bus, and the non-volatile cache system; a command output system that includes logic to output data transfer commands; and a data transfer system that includes logic to manage the flow of data directly between the non-volatile memory and the set of storage devices; and an arbitrator that arbitrates data traffic flow through the switch.