NV Memory ECC Encoding Using Pre-Calculation Information Rotation
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Solution Overview
Problem
Existing memory devices with MLC flash memory face instability issues and increased internal storage and costs due to the need for pre-calculated information in ECC processing, which affects access control and performance.
Innovation Solution
A non-volatile memory write method using data protection with pre-calculation information rotation, where the memory controller generates parity codes through pre-calculation information rotation type encoding, reducing the need for extensive internal storage and costs by utilizing partial matrices of the inverse matrix of the parity check matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-calculated information is stored in the controller IC to support various ECC processing specifications, then encoding delay is prevented and data protection is improved, but the internal storage space is forcibly increased causing costs to increase
Solution Approach 1:
The parity check matrix is divided into multiple sub-matrices (first sub-matrix, second sub-matrix, third sub-matrix), and the pre-calculated information is segmented into multiple groups corresponding to these sub-matrices. This segmentation allows the controller to store and process smaller portions of pre-calculated information separately, reducing the total storage space required while maintaining comprehensive ECC processing capability across multiple specifications.
Solution Approach 2:
The controller dynamically selects and processes different groups of pre-calculated information based on the specific ECC specification requirements. Instead of storing all possible pre-calculated information for all specifications simultaneously, the system activates only the necessary groups during encoding operations, making the storage and processing adaptive to actual needs and reducing overall storage requirements.
2Productivity
If pre-calculated information is stored in the controller IC to support various ECC processing specifications, then encoding delay is prevented, but the device complexity increases due to forced storage space expansion
Solution Approach 1:
The encoding process is segmented into multiple stages corresponding to different sub-matrices and their associated pre-calculated information groups. Each stage processes a specific portion of the data using the corresponding pre-calculated information, allowing for systematic and efficient encoding that maintains high speed while avoiding the complexity of a monolithic encoding architecture.
Solution Approach 2:
The controller loads and processes only the partial pre-calculated information groups that are necessary for the current encoding operation, rather than loading or processing all pre-calculated information at once. This partial action approach maintains encoding speed by having ready-to-use pre-calculated data available when needed, while reducing device complexity by not maintaining all possible pre-calculated information in active storage simultaneously.
3Quantity of substance
If MLC flash memory is used to increase recording density and reduce cost, then storage capacity is improved, but instability issues arise affecting access control
Solution Approach 1:
The system performs preliminary error detection and correction by calculating parity codes using the segmented pre-calculated information before data is written to or read from the MLC flash memory. This preliminary action allows potential errors to be identified and corrected in advance, compensating for the inherent instability of MLC cells and ensuring reliable access control despite the higher storage capacity and reduced cost.
Solution Approach 2:
The ECC processing system uses the calculated parity codes as feedback to detect and correct errors in the MLC flash memory data. By continuously monitoring data integrity through this feedback mechanism and applying corrections when errors are detected, the system maintains high reliability and stable access control while utilizing the high-capacity MLC flash memory.
Data Source
AI summary
A non-volatile (NV) memory write method using data protection with aid of pre-calculation information rotation, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory write method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through pre-calculation information rotation type encoding, wherein regarding a message: starting encoding a message to calculate a partial parity code according to the message and a transpose matrix of a part-one matrix within a parity check matrix; loading a partial matrix of an inverse matrix of a part-two matrix within the parity check matrix from a storage circuit; applying the partial matrix and its rotated version(s) generated through rotation control to generate and output a corresponding parity code; and writing into the NV memory.