Non-Volatile Memory Erase Control via Dynamic State Management

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Non-volatile flash memory erase operations cause significant latency, hindering host performance as they take longer compared to write and read operations, restricting concurrent processing during erase operations.

Innovation Solution

A method and system where a controller monitors the next command while performing an erase operation, determining its status and selectively continuing, suspending, or canceling the erase operation based on clock cycle counts within predefined steps, allowing for immediate execution of subsequent commands and optimizing erase time by managing erase operations across multiple address units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the erase operation is performed to completion before executing the next command, then data integrity is ensured, but system latency increases and host performance degrades

Engineering Contradiction:

Improvedata integrityVSAvoidsystem latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements dynamic control of the erase operation by introducing multiple executable states (continuable, suspendable, cancelable) that allow the operation to be adapted based on system conditions. The controller dynamically transitions between these states by monitoring clock cycles and command queues, enabling flexible management of erase operations to balance data integrity with system responsiveness.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent performs preliminary assessment of the erase operation status by counting clock cycles and determining the current executable state before allowing interruption. This preliminary action ensures that only safe interruption points are selected, maintaining data integrity while enabling timely response to new commands.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the erase operation is interrupted to execute the next command, then system responsiveness improves, but erase operation completeness may be compromised

Engineering Contradiction:

Improvesystem responsivenessVSAvoiderase operation completeness

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the controller continuously monitors the erase operation progress through clock cycle counting and maintains state information about the current executable phase. This feedback enables the controller to make informed decisions about whether to continue, suspend, or cancel the erase operation, ensuring that interruptions only occur at safe points where data integrity is maintained.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The erase operation is designed to be self-managing through its executable state mechanism. The operation carries its own state information and can autonomously determine whether it can be safely interrupted or must complete, reducing the need for complex external control while maintaining reliability.

Inventive Principle:

Principle #25Self-service

3Device complexity

If the host waits for the erase operation to complete before issuing the next command, then simple control logic is sufficient, but overall system performance degrades

Engineering Contradiction:

Improvecontrol logic simplicityVSAvoidoverall system performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent segments the erase operation into multiple executable states (continuable, suspendable, cancelable) based on clock cycle phases. This segmentation allows the controller to make granular decisions about operation continuation, enabling concurrent command processing without requiring overly complex control logic. Each segment represents a safe interruption boundary that maintains simplicity while improving performance.

Inventive Principle:

Principle #1Segmentation

4Loss of time

If the erase operation is monitored and conditionally interrupted, then latency is reduced and concurrency is enabled, but control logic complexity increases

Engineering Contradiction:

Improveerase latencyVSAvoidcontrol logic complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent uses periodic clock cycle counting to monitor erase operation progress and determine executable states. This periodic monitoring provides structured, predictable checkpoints for potential interruption without requiring continuous complex analysis. The clock-driven approach simplifies the control logic by providing natural, periodic decision points while enabling timely response to new commands.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS9443599B2Method of controlling erase operation of a memory and memory system implementing the same

Publication Date: 2016.09.13 SAMSUNG ELECTRONICS CO LTD

AI summary

A non-volatile memory and a method of controlling an erase operation of the non-volatile memory using a controller are provided. The method of controlling the erase operation includes beginning performance of the erase operation, monitoring a next command to be performed in the non-volatile memory while performing the erase operation, determining an erase status, and continuing, suspending or canceling the erase operation based on the determination result of the erase status.