Non-Volatile Memory Erase Control Circuit Using Preliminary Voltage Test
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Solution Overview
Problem
Non-volatile memory cells require increasingly higher voltage pulses for erase operations due to degradation over time, leading to inefficiencies and longer erase times as the number of cycles increases, necessitating a method to reduce the number of pulses required for effective erase operations.
Innovation Solution
A method involving a first voltage pulse applied to a non-volatile memory cell, with subsequent determination of the threshold voltage, updating a dedicated memory location, and verifying if the threshold voltage is below an erase-verify voltage to ensure successful erase operations, thereby anticipating and adjusting the voltage level to avoid the need for additional pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple voltage pulses are applied to perform erase operations on non-volatile memory cells, then the erase operation can be completed successfully despite degradation, but the erase time and operational complexity increase
Solution Approach 1:
The patent applies a preliminary test voltage pulse before the main erase voltage pulse to assess the memory cell's threshold voltage status. Based on the test result, the control circuit decides whether to apply the full erase voltage pulse or skip it, thereby avoiding unnecessary pulses and reducing erase time while ensuring reliable erasure when needed
Solution Approach 2:
The patent implements a feedback mechanism where the test operation result (comparing threshold voltage with test voltage) is used to control subsequent erase operations. The control circuit adjusts the erase operation based on feedback from the test voltage measurement, optimizing the number of pulses applied and reducing overall erase time
2Productivity
If the number of voltage pulses for erase operations is reduced, then erase speed and efficiency improve, but the risk of incomplete erase operations increases due to memory cell degradation
Solution Approach 1:
The patent performs a preliminary test operation before the main erase operation to evaluate the memory cell's current state. This preliminary assessment allows the system to determine the appropriate erase strategy, ensuring reliable erasure while minimizing the number of pulses needed for improved speed
Solution Approach 2:
The patent dynamically adjusts the erase voltage pulse parameters (amplitude, duration) based on the test operation results and memory cell degradation state. By changing these parameters adaptively, the system achieves complete erasure with fewer pulses, improving both speed and reliability
3Productivity
If test operations are performed to determine threshold voltage before erase operations, then the number of voltage pulses can be optimized, but the operational complexity and device control requirements increase
Solution Approach 1:
The patent designs the control circuit to perform multiple functions: it conducts test operations, measures threshold voltage, decides on erase strategy, and applies erase pulses using the same basic circuit architecture. This multi-functionality reduces overall system complexity while enabling pulse optimization through integrated control
Solution Approach 2:
The memory cell itself provides information about its state through its electrical characteristics during the test operation. The control circuit simply measures these inherent properties (threshold voltage) without requiring external complex diagnostic equipment, allowing the system to self-assess and optimize erase operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of voltage pulses needed for erase operations, enhancing the speed and efficiency of memory cell erasure while predicting and preventing failures, thus maintaining performance over the memory cell's life cycle.
Implementation Method 1
applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation
Implementation Method 2
sensing circuit configured to sense a conduction characteristic of each non-volatile memory cell indicating whether the threshold voltage of the non-volatile memory cell is less than the control voltage
Data Source
AI summary
A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.